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I'm building an SoC with my own soft-core, and I want people to be able to easily rebuild it using Xilinx webpack command-line tools. I'm using coregen's Clock Wizard to create a clock module, but coregen's output doesn't appear to be redistributable (the resulting verilog source claims to be confidential and proprietary information of Xilinx, who reserves all rights and doesn't specifically grant the right to redistribute AFAICT).

Is there a command-line/Makefile recipe somewhere for getting similar output from coregen that I can redistribute to my users?

http://github.com/atgreen/moxie-cores , btw.

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    \$\begingroup\$ What are the requirements of your clocking module? You can probably look at the Xilinx hdl users guide for the part you are targeting and directly instantiate the macros you need (mmcm or dcm and clock buffers). \$\endgroup\$ – davidd Nov 2 '12 at 17:54
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    \$\begingroup\$ I actually just figured this out. The coregen GUI will produce a file ending in .xco that appears to be redistributable. This file contains commands to feed coregen in batch mode (coregen -b FOO.xco -p PROJ.cgp). \$\endgroup\$ – AnthonyGreen Nov 2 '12 at 18:42
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    \$\begingroup\$ Could you post that as an answer? \$\endgroup\$ – drxzcl Jan 10 '13 at 12:12
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The coregen GUI will produce a file ending in .xco that appears to be redistributable. This file contains commands to feed coregen in batch mode (coregen -b FOO.xco -p PROJ.cgp)

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