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schematic

simulate this circuit – Schematic created using CircuitLab

The following is a circuit I got from a research paper and I am trying to analyze it. The inverter is a high speed inverting buffer whose output is always one. The circuit starts functioning when the inverter sends an output of zero. I will quote the sentences in the paper about the idle conditions (When inverter output is one)

"The output of inverter biases Q1 Such that its emitter Voltage is higher than the base voltage of Q3, thus cutting off the collector current of Q3. Capacitor C6 will have been charged to 5 volts through R17 with a time constant of about 5 us"

When the inverter ouput is zero,

"The inverter generates a fast falling edge and quickly turns off Q1 thus turning on Q2.The collector of Q2 draws a constant 23 ma from C1, thus discharging it at the uniform rate of 0.1 volts per nanoSecond"

My doubts :

1) How turning off Q1 can turn on Q2?

2) When Q2 is turned on, how the collector become constant taking 23 mA from C1?

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    \$\begingroup\$ 1 & 2/ The circuit is a so called "long tailed pair" I suggest you read up on that. Also the discharge statement is only partly true because at some point the discharge will stop. \$\endgroup\$ – Oldfart Dec 9 '19 at 5:47
  • \$\begingroup\$ @Oldfart But how can I calculate it to be 23 mA? Even if it is 23 mA, how can the capacitor current be constant? I can't see any circumstance I the circuit where linear discharging of capacitor is possible.. !! \$\endgroup\$ – Amalnath Satyan Dec 9 '19 at 5:56
  • \$\begingroup\$ why is V3 labeled as -5 V? ... is the polarity correctly oriented? \$\endgroup\$ – jsotola Dec 9 '19 at 6:05
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When the inverter output goes to 0V, Q1 effectively disappears from the circuit (the E-B junction is reverse biased) so you can just analyze Q2. When it is high, Q2 is off and it effectively disappears, so the capacitor charges through R1 towards +5V.

With the inverter output at 0V, the lower side of R4 is at -5V and the emitter is at about -0.6V if the transistor is active, so the emitter current (and the collector current assuming it's active) are about 4.3V/0.2K = 22mA.

There's a bit of current flowing through the 22K resistor which changes with the voltage and some other non-ideal things going on so it's not going to be exactly constant, but there's a region where the current is more-or-less constant so there is a more-or-less constant slope downward of about 100mV/ns at the collector of Q2, from the initial charge of the capacitor (5V or so) down to perhaps -500mV, after which the transistor saturates.

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Because Q2 base is at 0V, it is turned on when Q2 emitter goes to about -0.7V. Q1 is controlled so that emitter is higher than -0.7V or it lets voltage to drop to point where Q2 turns on.

Q2 is connected as constant current sink, and because Q2 base is at 0V, there is about -0.7V on emitter and thus about 4.3V over the 200 ohm resistor, 4.3V/200 is about 22mA and it is constant as supply voltage or Vbe voltage does not depend on capacitor voltage. Sure the current is less when capacitor is empty.

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