# Delayed ON level on pulse

I need a circuit which outputs a LOW level on power-up state. INPUT stays LOW. Once INPUT goes HIGH I need to run a delay which will set OUTPUT to HIGH after timed delay T (which is measured in seconds, should be configurable within 1-20s, accuracy aren't important). OUTPUT should stay HIGH until complete power-off. Rest INPUT level transitions are ignored. Like this:

TTL levels. I've did it this way in simulation with 7474 trigger and 4584 inverting Schmitt trigger:

The only difference that button LOW level triggers transition, but it can be inverted with other inverter IO on same 4584 I guess.

Will this work in real hardware or maybe someone could suggest a better circuit for my needs?

EDIT: Based on @elliot-alderson answer, I've modified my schematics to make sure both flip-flops will output LOW level at power on and no inputs are floating: I've also changed button position to simulate original low-to-high transition input as drawn on my 1st diagram.

• This is just a copied canned comment to let you know that what you're trying to build from discrete analog components (possibly incorporating Opamps and/or NE555) is a digital control problem and thus can easily and with lower parts count be solved with a microcontroller with really minimal firmware to write. (Source: Marcus Müller) Dec 9, 2019 at 9:15
• @Huisman I can build it with simple MCU easily. But for personal reasons I would prefer MCU-less solutions. Helping a friend who asked for this circuit. He can build a circuit from locally available parts. But flashing MCU firmware could be an issue for him. Dec 9, 2019 at 9:18
• @Huisman, unfortunately there are costs and production overheads that come with microcontrollers, no matter how small the program. Depending on the industry, these go from light (student or do-what-you-like small firm) to severe (aviation, defence). For electronics engineers, it highlights the difference between electronics (the circuit) and engineering (the deploying and supporting). You really have to compare the actual lifetime costs, not the component costs. Dec 9, 2019 at 9:31

It's raining and I'm bored. Here is a reworked version of the OP's circuit. Using the CLK input for U1B (or the positive-true Set input of the 4013) eliminates the inverter. R5 adds a little hysteresis to the clock input signal and eliminates the need for a Schmitt trigger gate.

• Wow! Thank you so much for all the solutions provided. Dec 10, 2019 at 12:46

This can be done with one quad NOR gate. Two gates form an adjustable monostable, and two gates form a S-R flipflop with a power-on reset.

U1A and B form a true monostable that ignores all switch bounces after the first positive edge. U1C and D form the output flipflop to hold the output state after the monostable times out and triggers it. U1 pin 3 rests high after power-on, which would create a false signal at U1 pin 13. The added C3-R3 differentiator has a time constant that is five times shorter than the power-on reset pulse from C4-R4, so C3 has time to charge up before the flipflop is enabled. In this way, the flipflop ignores the monostable high output state on power up, but responds to the high state at the end of the delay period.

Once the flipflop is set after the first time-out period, all subsequent inputs are ignored. Power should be off for 1 sec. minimum to reset C1.

How can you be sure that the second flip-flop will always wake up in the zero state when power is applied? Is that specified in the data sheet? You may need to add more circuitry to ensure that this happens. Is it OK if the output is high for a short time after power is applied?

The feedback circuit from U2:A to U1:A seems unnecessary. You don't care if the second FF gets multiple clock edges because its input is always a logical 1.

Driving CMOS logic from TTL logic can be unreliable, because the $$\V_{OH}\$$ produced by TTL tends to be pretty low. I would consider using CMOS flip-flops instead.

The delay time will indeed be imprecise. Capacitors have a large tolerance, and the leakage through the capacitor may be significant compared to the current through the 100k resistor.

• I am not sure which are the initial state of 2nd FF if both SET/RESET are at HIGH (internally pulled up). Datasheet doesn't states anything about it, but Proteus simulation models it as LOW level output in this condition. But probably this needs something to do about because that is NOT OK for me if the OUTPUT will pulse HIGH during startup. Feedback to U1:A are required to pull U1:B CLK back HIGH as data are latched during LOW-to-HIGH transition, not vice versa. Instead I could connect U1:A output to U1:B SET pin instead of CLK, which will set its output HIGH on HIGH-to-LOW transition. Dec 9, 2019 at 14:07
• I've modified my schematics based on your first 2 paragraphs. Could you please take a look? Dec 9, 2019 at 14:32
• I don't think the second flip-flop serves any purpose at all now. You could just use a second section of the 4538 instead. Dec 9, 2019 at 15:03

Elliot Anderson makes a good point. Here is the original circuit reduced to just three inverters.

Looks like my solution turned out to be similar to @AnalogKid 's last one

Except I used a diode switch to latch, while his looks like a relaxation oscillator.

Was just watching father & son PGA goff and goofing around here.

Cost \$0.25 in volume

• A Schmitt-trigger based relaxation oscillator usually has only one inverter, and utilizes negative feedback for the timing components; my circuit uses positive feedback to create a latch. I started with a diode, but the resistor has worked better for me in the past. Your 4-inverter version is exactly where I started, then I got the idea to flip over the timing capacitor and eliminate one inverter. Dec 10, 2019 at 1:12
• I see it ..now. Dec 10, 2019 at 1:46