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As far I know there are two important points related to power-supply decoupling capacitors. First the placement be less than 3 cm from the digital IC. Second the power tracks route pass through this capacitor first and then connect with the digital IC power pins or balls.

If I have problem in fulfilling both requirements especially in the case of BGA package then where can I do some compromise, in its placement or in its power-trace routing so that it causes lesser harm to the operation?

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  • \$\begingroup\$ There is no single distance for a decoupling device; it depends on the the edge rates of the IC for both internal and external signals. It might be as little as 10mm or as much as 50mm or even both (local and bulk). If you specify the IC and operational modes we may be able to assist. \$\endgroup\$ Dec 9 '19 at 11:04
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For any type of decoupling application, closer is better.

"... the power tracks route pass through this capacitor first and then connect with the digital IC power pins or balls."

That's better than having the power tracks go to the BGA first, then to the cap. Note that in many applications, the small ceramic decoupling caps are mounted on the back side of the board, directly under the BGA just outside of the ball field.

Like Peter Smith said, a lot depends on the speed/edge rates of what the device is doing. To really do this right, you would need to build a model of the PDN (Power Distribution Network) and simulate that with your application.

Finally, we could give a more definitive answer if you wold provide some more details of you application, such as:

  1. Clock rate of the device
  2. Device type, part number, etc
  3. Size of the package, how many balls
  4. Number of IO that switch, and at what rate
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  • \$\begingroup\$ 1) 50 MHz, 2) Spartan 6 FPGA, 3) 676 balls 4) Approx 100 IOs are switching. All of them are not switching at the same rate. The fastest would be approx. 10 MHz. \$\endgroup\$
    – alt-rose
    Dec 9 '19 at 12:28
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    \$\begingroup\$ That doesn't sound like a very stressing situation. With the Spartan, most of your dynamic current is going to come from the IO switching. That being the case, you want to use the slowest/weakest IO drivers in the Spartan than you can get away with. Then, you want a combination of 0.01 uF ceramics, 0.1 uF ceramics, and a couple of 2.2 uF or 4.7 uF caps near the part. The smaller ceramics you want to get as close to the power and GND balls as possible. Note that this is just a rule-of-thumb recommendation. \$\endgroup\$
    – SteveSh
    Dec 9 '19 at 13:09
  • \$\begingroup\$ So if I am stuck and can only do one of these, good placement OR good routing of the decoupling capacitors.. then which one is preferable? \$\endgroup\$
    – alt-rose
    Dec 10 '19 at 11:10
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    \$\begingroup\$ IMO, you want the placement/routing that minimizes the trace lengths between the capacitors and the power/gnd pins of the FPGA. Think of this as trying to keep the loop area that the current flows in (cap->FPGA->GND->cap) as small as possible. \$\endgroup\$
    – SteveSh
    Dec 10 '19 at 12:00

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