# How to calculate how much high ESR capacitance to smooth impedance spikes?

I am making a 3.7V to 5V voltage booster with 25x 100uF ceramic capacitors on the input and output (with room to add more if needed). I've been warned that having such high capacitance with such low ESR can cause impedance spikes/oscillations on the order of 10's of volts when I first connect it to power, which can ruin my parts.

How do I calculate how much capacitance, and at what ESR I need to smooth the spikes? Is it just a matter of trial and error with an oscilloscope? I'd like to add some low value resistors in series to the ends of a few of the caps' but I don't know what value resistors to get, or how many I will need.

• Why do you need such high C values? and what current pulse rate with L did you have in mind? – Tony Stewart Sunnyskyguy EE75 Dec 10 '19 at 1:59
• @TonyStewartSunnyskyguyEE75 shooting for 15A max that’s why :) I used Webench to help design and that’s what it recommended. It’s at ~200kHz – Ryan Dec 10 '19 at 2:01
• It is a simple damping issue. The wire between the battery and your converter has some inductuance. When you first connect the battery to the converter, there is potential for input overshoot (because you have a step voltage applied to an LC circuit). If the battery connection is very short and direct, you may not have any problem with overshooot. In order to calculate how much esr you need, you will need to know the inductance between battery and capacitors. Without that it is impossible. Personally I would simulate, not calculate. – mkeith Dec 10 '19 at 4:38
• Another way to fix this is by using an inrush limiter of some sort to charge the caps slowly. Once they are charged, it will act like a short circuit. Even if you sort out the damping, you may still have a very large inrush current which could lead to sparking, or maybe even trip the over-current protection of the battery protection circuit. – mkeith Dec 10 '19 at 4:40
• If you haven't already, please read this (App note AN-88): analog.com/media/en/technical-documentation/application-notes/… – mkeith Dec 10 '19 at 4:46

For a SMPS 3.7 to 5V, 15A your load is 5V/15A= 333 mΩ

For ripple to be 1% of 5V or +/-50mV your bulk cap ESR must be 3.3mΩ

Typically you can expect ESR*C <=10us for low ESR and > 100us for general purpose e-caps in this size range.

Thus using above Rule of Thumb for cheap low ESR, T = ESR * C = 10us = 100uF * ESR , thus ESR= 100 mΩ Therefore you might need 33 Caps or get 25 Caps with ESR < 25/33*10 = 7.5mΩ
If you want < 1% ripple then go for the best ultra-low ESR e-caps T=<2us

There is a matter of size and rms ripple current rating at some temp rise and MTBF at rated temperature. You want to use at least 25% derated values. So with 15Adc rms ripple current, est. the ratings will be shared by 25 caps or ~ 1Arms min rating per cap.

You may want to consider 1uF caps as well.

Examine the RLC parts as a Low Pass filter and examine the Q and harmonic rejection.

Inductor peak currents may be 35A also of concern.

Phase lag of LPF reduces phase margin of loop filter step response.

Arrange for lowest inductance.

## update

Simulation to validate assumptions previously stated Just a quick & dirty simulation of a SMPS with a slider for ESR.

Bottom Line - -

If you are skilled in understand Q , impedance matching of RLC and the effects of phase shift on feedback of 2nd order filters, you will realize these are not compatible properties. The 180 deg phase shift of an RLC filter interferes with the step response stability of a closed loop voltage regulator unless you use feed forward compensation, Current feedback in addition to voltage ratio feedback or error to Vref ( here simulated crudely with a Zener).

Thus ripple noise is unavoidable inside the closed loop 2nd order loop. However ripple filtering you do outside the loop has no effect on stability.If I could demonstrate this, I would show ESR going to uOhms with ripple reducing meanwhile Q has risen >>1 and caused phase margin to drop very low and disturbances to load cause incredibly bad over/undershoot at the loop filter peak resonance frequency.

Thus too low ESR results in low phase margin and instability but low ripple. Expect to need phase lead compensation with ESR+LC filter Q near 1.

• Does this answer cover LC inrush as well? I’m re reading it many times to understand it best I can 😁 – Ryan Dec 10 '19 at 8:19