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I have an SR flip-flop such as above, and I'm to determine whether it's positive-going or negative-going. How can I do that? I understand that edge-triggered flip-flops' output only change upon edges of clock. But I don't know how to determine which one.

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  • \$\begingroup\$ This arrangement is usually called a master-slave flip-flop. It's not really edge-triggered although the output doesn't change until the clock goes low. \$\endgroup\$ – Kevin White Dec 10 '19 at 23:31
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Just look at the slave flip flop in your schematic, IC2. When will its outputs, Q and -Q change, relative to the clock?

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The IC1 Gates inputs when CP="1" then IC2 gates those outputs when CP="0" to produce the change in output. When CP="0" IC1 is disabled so input changes cannot affect the output.

Thus you have a positive CP enable state internal latch going into a negative edge CP output register.

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