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What's wrong with the following code? The array "FIFO" is declared correctly, but an error appears. Can you please help how to fix this?

module fifo(
    input clk, 
    input [7:0]data_in ,
    output reg [7:0] FIFO [0:8]
);

integer i;
always@(posedge clk) begin
       for(i = 8; i > 0; i=i-1) begin
          FIFO[i] <= FIFO[i-1];
       end
       FIFO[0] <= data_in;
end
endmodule

Error (10773): Verilog HDL error at fifo.v(29): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions

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Exactly what it says: you have a two-dimensional output port which is an unpacked array.

This is a packed array: output reg [7:0] FIFO
This is an unpacked array: output reg FIFO [0:7]

Therefore your two-dimensional array is an unpacked array.

Verilog allows only packed arrays for ports.
If you want two or more dimensions you need to compile with System-Verilog.

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