I do low-speed circuit design for microcontrollers and such (usually at less than 20 MHz), and now I'm getting started on some more high-speed circuits. What I want to know is:
What considerations need to be made for traces in high-speed circuits?
Do I have to impedance-match each line between two high speed devices?
Do all the traces need to be the same length?
Is there a good reference for these rules?
Can this be done using open-source circuit design tools (gEDA and company)?
(I should say at the outset that I have some experience with boards in the 100 MHz range, but I'm far from an expert.)
The canonical reference is High-Speed Digital Design by Johnson and Graham. Johnson also wrote a more advanced sequel, High-Speed Signal Propagation, in 2003.
You can lay out any board with gEDA and company, but it can become arbitrarily difficult to the extent that I would seek a better tool if you can get it. Matching the lengths of many traces by hand gets tedious quickly.
As for what you actually need to do with traces, here are the things I watch out for:
The length of traces starts mattering once your traces are longer than 1/6 of the rising edge of a digital signal. For a rise time of 1 ns on a typical PCB, the rising edge spans around 6 inches, so you want your traces to be less than 1 inch in length.
You want to match the termination of your traces to their characteristic impedance to prevent reflected signals. In practice, this means either putting a resistor to ground right before the trace reaches its destination or putting a resistor in series at the start of the trace. I've found the diagrams in chapter 12 of Analog Electronics by Crecraft and Gergely to be worth staring at for extended durations: http://books.google.com/books?id=lS7qN6iHyBYC&lpg=PP1&ots=cg6ZMM2GI1&dq=analog%20electronics%20crecraft&pg=PA296#v=snippet&q=propagation%20of%20a%20pulse&f=false Manufacturer's datasheets will sometimes have recommended termination schemes.
As your signal speed increases, you have to start worrying about voltages induced in neighboring traces due to mutual inductance and rapidly changing currents (V = L * di/dt). People call this "crosstalk." This means that you need to spaces traces away from each other, use a ground plane under all your traces, and/or put ground traces ("guard traces") between the traces you're trying to isolate.
That's all that I actually worry about in practice.
For high speed digital signals, you'll want to match the impedance of the trace to the output impedance of the signal's output driver. Many signal transmission lines also require termination. This reduces reflections and inter-symbol interference. The trace's impedance is determined primarily by it's width and the PCB stack-up, but the signal return path also plays a role. Switching layers or routing a signal across a split ground plane will create impedance discontinuities and will degrade the maximum speed at which the link can operate.
Trace length matching requirements will be driven by the timing requirements of the bus protocol used by the signals. E.b., a DDR memory interface will require that the DQ (data) signals arrive within so many pico-seconds of the DQS (strobe) signal. A rough estimate of the mismatch can be calculated from the trace length mismatch and the propagation delay of the transmission line. Signal integrity engineers create more precise analyses of timing skew by running simulations of the routing topology and models of the I/O drivers.
A great reference on the subject is Dr. Howard Johnson's book "High Speed Digital Design: A Handbook of Black Magic" (http://www.amazon.com/High-Speed-Digital-Design-Handbook/dp/0133957241)
Jason
This all really depends on what you mean by "high speed".
The most important factor in determining whether you need termination is the amount of time it takes for a rising edge to propagate. If your rise time is 100 ps, then it doesn't matter if you're 100 MHz or 10 MHz, reflections will still hurt you. But reflections are only a problem when you reach "transmission line" lengths. I think that's something like...for every 300 ps of rise time you can go about an inch without termination. So for a rise time of .9 ns, you can go about three inches.
As far as the impedance of traces, you should google "microstrip". You will need a solid ground plane underneath the trace. Then, the distance of the trace from the plane (determined by board stackup), and the width of the trace, should largely determine trace impedance. Many PCB design tools will automatically calculate the trace impedance for you.
You don't need to make the traces the same length unless your circuit requires it. For example DDR memories require it within a certain amount and differential traces require it.
The standard for simulation is HyperLynx (by Mentor). LineSim does it pre-layout; BoardSim does it post-layout.
