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What can be the possible DC and Transient analysis for OR gate using CMOS and the threshold voltage like we do for NAND or NOR?
Or what can be the possible calculation to decide the W/L of PMOS and NMOS in designing an OR gate?

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  • \$\begingroup\$ Welcome to EE.SE - what research have you done to attempt to answer your question? We expect those with questions to have put some effort into answering their query and ask about the parts they are having difficulty with. \$\endgroup\$ Dec 12, 2019 at 9:39

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You can't make the OR function in a single static, fully-restoring CMOS gate so the same analysis that you use for a NOR won't work. The OR function requires, for example, a NOR gate followed by an inverter.

Show us the circuit you want to analyze. Explain exactly what sort of dc and transient behavior you want to calculate.

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  • \$\begingroup\$ I just want to simply analyze OR 2X1 circuit using CMOS. I can perform any analysis and decide the parameters,but major part is to decide W/L ratio and then simulate the circuit. Maximum height of standard cell can be 2.88 um. No restrictions on DC or transient analysis. I am thinking of considering Vth as Vdd/2 and then calculating the W/Land draw the schematic. but for that, i require Vth equation. \$\endgroup\$ Dec 12, 2019 at 21:38
  • \$\begingroup\$ Do you have the Vth equations for a NOR gate and an inverter? An OR gate will consist of a NOR gate followed by an inverter, so just combine those equations. \$\endgroup\$ Dec 12, 2019 at 22:47
  • \$\begingroup\$ Yes. In the below given link is the complete analysis of NOR and INV Gate and Threshold voltages is been derived for them. icsd.aegean.gr/lecturers/nkonofao/… \$\endgroup\$ Dec 12, 2019 at 23:54

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