# Preparing custom / arbitrary sequence counter

I know following types of counters:

Asynchronous counter

Clock input of each flip flop is output of earlier flip flop.[ref]

Synchronous counter variant 1: with ANDing for flip flop inputs

Note that in this variant of synchronous counter, we have ANDed outputs of earlier flip flops to form input of next flip flop. [ref]

Synchronous counter variant 2: with ANDing for flip flop clocks

Note that in this variant of synchronous counter, we have ANDed outputs of earlier flip flops to form clock of next flip flop. [ref]

I know how we can prepare custom / arbitrary sequence counter with synchronous counter variant 1. These two pages give examples: 1, 2

Consider the diagram from second page:

So it seems that to obtain arbitrary sequence, we need to form inputs of flip flop by some combinations of outputs. Does that mean, we cant construct arbitrary sequence counter following other two approaches, asynchronous counter and synchronous counter variant 2, as in both of them inputs of all flip flops are tied to HIGH logic?

• Your "synchronous counter variant 2" is really an asynchronous counter. Synchronous means that ALL FFs get the exact same clock. – Dave Tweed Dec 12 '19 at 11:36
• I believe synchronous mean flip flops change their output states together. It might be achieved by different implementations and not necessarily with the same clock applied to all flip flops. I may be wrong as I am not electrical / electronics major. But I referred to the mentioned reference book. I dont know if its wrong in the book itself. Also I know that most sources / books dont really discuss this approach. But I feel variant 2 circuit output too behaves like synchronous counter. Nevertheless, I believe, the question stays valid. – anir Dec 12 '19 at 12:07
• As noted by Dave Tweed, synchronous counters get exactly the same clock; aribitrary sequences are usually done (for JK types) by changing the J and K inputs prior to the next clock. – Peter Smith Dec 12 '19 at 12:08
• Please note that, in variant 2, all flip flops still gets same input clock, just that it is ANDed with outputs of earlier gates. So I guess it should still behave like sync counter. Also from the timing diagram it looks like sync counter. I can confirm that the book does indeed specify it under synchronous counter section. The book pdf is available online, but I dont know if it is rightful to link it here. You can find relevant page here. – anir Dec 12 '19 at 12:28
• (continued from earlier comment) @PeterSmith by "aribitrary sequences are usually done (for JK types) by changing the J and K inputs prior to the next clock", do you mean arbitrary sequence counter cannot be prepared by two methods: async and sync variant 2 (regardless of whether it is really sync or async)? – anir Dec 12 '19 at 12:30