I'm reading ZipCPU's tutorial and got confused. Specifically, I'm referring to this page.
To transcribe the Verilog code:
input wire i_S; input wire [7:0] i_V; output reg [7:0] o_R; always @(*) if (i_S) o_R = i_V;
I can understand that if
o_R is declared as a
wire, then a latch will be inferred as wires have no memory, and thus some external memory is required to keep the previous value. However,
o_R is a register here, and registers can keep their state. For example, we can simply connect
i_S to the "write enable" pin of the flip-flop corresponding to
o_R, so why do we have a latch now?
As a bonus, why is a latch, rather than a flip-flop, inferred in such a situation? I'm under the impression that they basically serve the same purpose.