I've briefly flirted with FPGA development in Verilog, and its admittedly somewhat slower than writing the same program on an MCU (defining pins, and their behaviour, no modules available, etc). I've therefore been on the lookout for a software that can help me design using block diagrams or something more visual. I've heard of Mathworks Simulink, and the FPGA/ASIC line of tools from Synopsys, Cadence, Mentor Graphics, etc, but since I've never had a chance to get my hands on these I don't really know how intelligent or visual they are. Have you ever heard of such a software with such a feature set? and would block diagrams have any advantages over designing textually in Verilog?
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\$\begingroup\$ No-one ever seems to ask for a block diagram tool when writing software. Why is it so for using HDLs? \$\endgroup\$– Martin ThompsonNov 5, 2012 at 15:09
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3\$\begingroup\$ @MartinThompson, people ask for, and produce, graphical software tools all the time. LabVIEW and Simulink are some commercial examples, there's the open source Umbrello and Eclipse Modeling Framework, and the general category of CASE and Model-Driven Architecture tools. Graphical tools can be useful; the problem arises when people see them as a way to avoid the intimidating syntax of textual languages, when it's really the semantics of the problems that makes development hard. \$\endgroup\$– TheranNov 5, 2012 at 22:59
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\$\begingroup\$ @Thernan - yes, I'm well aware of that. I just am aware of very few questions on SO (and other fora) along the lines of "I'm just starting out in C/Python/Java - what's a good block diagramming tool for those languages" compared to the similar question with HDL in it. Maybe I'm not looking hard enough :) \$\endgroup\$– Martin ThompsonNov 6, 2012 at 10:14
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3 Answers
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Altera has a free version of their IDE (Quartus II Web Edition) products/software/
I mean you still have to write code, but once its written you can use the symbols to abstract and get like a block version of the entity, and graphically interface between blocks (via buses etc.)
Also, Would a program like LogiSim work better? At least if it had some kind of VHDL/Verilog extension!
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You can use Xilinux or Altera. Both have schematic entry tools that enable you to draw logic blocks and connect them with wires. But it is typically easier to do it with Verilog.
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Here is my advice to programming FPGA's graphically: Don't.
There are two ways to use graphical design entry: 1. doing all of the logic graphically. And 2. doing a mixture of graphical and text based design entry.
It is not practical to do the whole thing graphically. There are logic designs that are simply too complex to do graphically, but are super easy using VHDL or Verilog. Complex state machines are a good example, but in reality most things are easier to do in VHDL or Verilog once you know the language.
While doing a mixed text/graphical entry is possible, it really doesn't offer much advantage. Once you know VHDL/Verilog good enough to do the text based parts of the design, the graphical parts offer no advantage of speed or understandability.
There are other disadvantages of doing a mixture as well. For starters, your design is not easily ported to other FPGA architectures. You have to master two different tools (text editor and graphical design entry). People who look at your design will have to understand both. It is harder to use normal text based development tools like version control systems, diff, make, etc.
In the end, using a graphical entry is just an added pain that doesn't prevent you from having to master VHDL and/or Verilog.