I am trying to calculate the output filter impedance and the phase difference of the inverter that I am designing. enter image description here However not sure how to construct a formula for both the output impedance and phase difference. I know that for series RLC network both parameters can be calculated as follows: enter image description here


Current direction alternates, but for a single cycle say it flows into AC_L and out of AC_N with a voltage source connected between them. The output is considered between the two points. Therefore, I want to know the impedance of the total network were (R || C) in series with L. I can see how my formulated question is no good since i did not specify the termination points. Apologies


  • \$\begingroup\$ "of the inverter I am designing"? That's a filter, not an inverter. \$\endgroup\$ – TimWescott Dec 13 '19 at 23:07
  • \$\begingroup\$ Yes it is only a filter stage that I am referring to here. not the full design. \$\endgroup\$ – RytisBe Dec 13 '19 at 23:12
  • \$\begingroup\$ Do you mean the phase difference from input to output of the unloaded filter? Do you realize that there isn't one expression for both output impedance and phase lag? \$\endgroup\$ – TimWescott Dec 13 '19 at 23:16
  • \$\begingroup\$ I never said that there was a single expression that can represent both. I already indicated that there are 2 unique expressions for RLC series network output impedance and phase difference. And yes "the phase difference from input to output of the unloaded filter" and the impedance of the total network is what I am looking for. \$\endgroup\$ – RytisBe Dec 13 '19 at 23:23
  • \$\begingroup\$ When you are design a converter, ESR, ESL, RdsOn are load R are all critical, so use a simulator. I like Falstad's where you will search my answers for Falstad \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Dec 13 '19 at 23:41

This interactive calculator will give you the phase response (amplitude and phase delay responses too). It will also show the overshoot for a step response: -

enter image description here

I have chosen approximate likely values of 10 mH, 100 uF and 10 ohms to help you get started. You can do the rest and you can move the X axis pointer along using the controls. If you search elsewhere on that site you will find the formula.

The output impedance is the parallel sum of the three impedances XL, XC and R.

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  • \$\begingroup\$ Well not really. R and C are in parallel and RC is in series with L --> [(R||C) - L]. I can't treat them as all in parallel. \$\endgroup\$ – RytisBe Dec 14 '19 at 13:30
  • \$\begingroup\$ @RytisBe no, you are incorrect. The voltage source at the input has zero impedance hence, to calculate the impedance looking back into the output node, L is grounded thus R, L and C become in parallel. Simple circuit theory really. And don’t argue about it lol! \$\endgroup\$ – Andy aka Dec 14 '19 at 16:45
  • \$\begingroup\$ What you have described is the input impedance to the filter as would be seen by the voltage source V1. \$\endgroup\$ – Andy aka Dec 14 '19 at 17:42
  • \$\begingroup\$ I appreciate your help, but I need to understand more before replying "arguing" back. In fact I will draw out on a paper what I am really trying to do. \$\endgroup\$ – RytisBe Dec 14 '19 at 17:54


simulate this circuit – Schematic created using CircuitLab enter image description here


The output impedance for your chosen circuit replaces the supply as a 0 Ohm connection ,then you get a parallel RLC circuit Zout=R//XL(s)//XC(s) which has infinite Q with no load.

In reality your SMPS has a switch that when open will have a non-zero resistance and when open may be a different part like a complementary switch or a diode with a different resistance.

But you may appreciate an interactive filter application that runs in any browser using javascripts.

Although very simple , you can choose from Active or passive Filters and display log gain, Phase, Roots of built-in filters and create transmission line filters.

Real filters have ESR,ESL, and parasitics. Loads affect the Q and challenge closed loop stability in SMPS. The other Falstad site allows time domain interactive analysis with custom FETs. It is also very simple yet powerful with many scope interactive traces allowed.

enter image description here

Below, I switched to Butterworth and enabled Root plots and phase, changed to cutoff @ 200kHz and displayed the attenuation by mouse cursor 12dB down 1 octave up @ 400kHz. enter image description here

This question could also have been easily answered with a web search "RLC parallel impedance" in more detail and less time. Please learn how to learn.

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  • \$\begingroup\$ Same as well here. You provide me with simulations and bode plots, but I need a mathematical expressions not the final results. \$\endgroup\$ – RytisBe Dec 14 '19 at 14:25
  • \$\begingroup\$ You need specs to have an expression .... are you saying you have no idea how to compute Zout=R//XL(s)//XC(s) ? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Dec 14 '19 at 15:58
  • \$\begingroup\$ I do know how to compute RLC parallel network, but I think it is not exactly what I am dealing here with. I wonder now, would it have been better if didn't ground the voltage source. I will update the question with a relevant section of an actual circuit. \$\endgroup\$ – RytisBe Dec 14 '19 at 17:57
  • \$\begingroup\$ Do you not know impedance of a capacitor or inductor? Easy to find? This is exactly your answer . Also for impedance. ignore DC and source becomes an AC 0 Ohm jumper \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Dec 14 '19 at 18:08

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