There are plenty of questions about how to size decoupling capacitors in digital systems, but I have not found the answer to my specific question.
They are some capacitances that are usually put externally in circuits with MCUs or other digital circuits between GND and VDD. Their main role is that of reducing the power supply fluctuations. One of these kind of fluctuations is the so called ground bouncing, which is the drop of the voltage supply on the parasitic resistance of the supply line during the instants in which transistors absorb more current. It may be seen as a drop of VDD, or a rise of VGND, as shown in this graph.
I have seen in some datasheets (and the same has been written in some other questions) that usually they are chosen with 0.1uF capacitance (and surely not more than 1uF). But I do not understand the specific reason of putting this upper bound. I understand that their capacitance must be quite high (high capacitance = high smoothing effect), but why do we stop at 0.1 or 1uF? Why not 10uF, 100uF, ideally infinite F?
For instance, in stabilised DC voltage supply, I have always used (in parallel, after Graetz Bridge and before the voltage regulator) an electrolytic capacitor of 15.000 uF, and its purpose was, at least conceptually, similar to that described before.