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From the worst to the best design due to impedance parameters that affect the signal i would do it as a) > b) > d) and c) because c) is the one with the lowest lenth and lowest curves, am I right?

EDIT: I know that all the designs could work but I want to know which one is the best one and the reason for that.

enter image description here

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  • \$\begingroup\$ all can be made to work \$\endgroup\$
    – Neil_UK
    Dec 15 '19 at 15:02
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    \$\begingroup\$ I think you should add more design parameters. If the board only does DC, you're likely trying to optimize a design from 99.9999% to 100% \$\endgroup\$
    – Huisman
    Dec 15 '19 at 15:08
  • \$\begingroup\$ What is the frequency of interest here? Is there a ground or reference plane above or below the trace? \$\endgroup\$
    – SteveSh
    Dec 15 '19 at 15:49
  • \$\begingroup\$ @SteveSh The only info I have are those pics, I just need to know what the best trace and the worst one between those resistances \$\endgroup\$
    – FabioEEC
    Dec 15 '19 at 15:56
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    \$\begingroup\$ I would argue C is shorter than A, so at DC C might be superior. At non DC my guess is A becomes Superior. This kind of looks like homework are you familiar with the homework policy? \$\endgroup\$
    – MadHatter
    Dec 15 '19 at 16:09
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It's very unlikely that there's any design where one of these configurations would work and the other three would fail.

If you're designing this to carry a low speed, high current signal, then it would be better to either Move the two ends of the trace closer together (i.e. move R2 closer to PL1) or use a wider trace, or use a parallel trace on another layer, or ... If no other changes are possible, then possibly c is better than the other options, but more likely they'll either all fail or all work.

If you're designing to carry a high-speed signal, then it would be more important to be sure that your ground-plane beneath the trace is unbroken, that the trace width is correct to provide controlled impedance, that the trace-to-ground separation on the top layer is not affecting characteristic impedance, that the connectors are adequate for your frequency content, etc., etc., before worrying about the difference between the different trace paths.

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