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I'm struggling to understand the diference between a Latch and a SR Flip Flop, I know that a latch is level activated, and the SR Flip Flop is edge activated but if the circuit is the same, why is the behavior diferent?
I watched this video from Neso Academy, I really don't know why the latch becomes edge active if I use a clock.
If i send a 1 the latch is active, so why isn't the SR flip flop active when the clock is 1?
Am I missing something or is there an error in the video?
The only time when SR latches are edge-sensitive is the release of SR input contention.
When both Set and Reset are active then both outputs Q & Q* are asserted "1". Then after the 1st input {S,R} edge is removed from the active state, only the corresponding output {S=>Q, R=>Q!} will change.
A clock enabled SR Latch is a MISNOMER if called a Flip Flop as it not a Flip Flop {D,T or JK} Also this would cause an unstable output if both S=R=active when Clock enable goes low.
Conclusion: Youtube video is wrong.
clock in place of enablestatement is kind of ridiculous in that context ... it is exactly the same thing .... perhaps what should have been said isif you think of the signal as a clock instead of enable\$\endgroup\$ – jsotola Dec 15 '19 at 21:02