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I'm struggling to understand the diference between a Latch and a SR Flip Flop, I know that a latch is level activated, and the SR Flip Flop is edge activated but if the circuit is the same, why is the behavior diferent?

I watched this video from Neso Academy, I really don't know why the latch becomes edge active if I use a clock.

If i send a 1 the latch is active, so why isn't the SR flip flop active when the clock is 1?

Am I missing something or is there an error in the video?

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  • \$\begingroup\$ if the circuit is the same, then the behavior cannot be different \$\endgroup\$ – jsotola Dec 15 '19 at 20:12
  • \$\begingroup\$ exactly that's why I don't understand the video, he said "the circuit will act as a Flip flop when we have clock in place of enabled" I'm not sure if I am missing something because Neso Acadamy seems to be a good channel \$\endgroup\$ – Tiago Oliveira Dec 15 '19 at 20:19
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    \$\begingroup\$ The term 'latch' and 'flip-flop' are rather mixed up. Even in wikipedia they talk about "a flip-flop or latch". Engineers, like me, who have to deal with registers and latches make a clear distinction. What they show in that video is not what we experts call a 'latch'. So again: be careful what you find on YouTube. \$\endgroup\$ – Oldfart Dec 15 '19 at 20:19
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    \$\begingroup\$ I suggest you ignore the video and look for other resources. Note that the terms "latch" and "flip-flop" are not standardized. \$\endgroup\$ – Elliot Alderson Dec 15 '19 at 20:29
  • \$\begingroup\$ the clock in place of enable statement is kind of ridiculous in that context ... it is exactly the same thing .... perhaps what should have been said is if you think of the signal as a clock instead of enable \$\endgroup\$ – jsotola Dec 15 '19 at 21:02
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The only time when SR latches are edge-sensitive is the release of SR input contention.

When both Set and Reset are active then both outputs Q & Q* are asserted "1". Then after the 1st input {S,R} edge is removed from the active state, only the corresponding output {S=>Q, R=>Q!} will change.

A clock enabled SR Latch is a MISNOMER if called a Flip Flop as it not a Flip Flop {D,T or JK} Also this would cause an unstable output if both S=R=active when Clock enable goes low.

enter image description here

Conclusion: Youtube video is wrong.

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