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In the ARM Cortex-M3 processor core, the memory map contains: a Code region, SRAM and a RAM. What makes the use of the code region different than the other memories? In addition, what is the nature of the (memory) of the code region?

Thank you.

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Instruction fetches from the Code space are accessed via the ICode bus. Access to the SRAM and External RAM space are via the system bus. These regions have different characteristics regarding cache support. This is actually a broad topic and you should read the ARMv7-M Architecture Reference Manual for the details.

As to the "nature" of the memory, Code memory is generally assumed to be non-volatile and on-chip. The SRAM region is assumed to be on-chip but the External RAM is assumed to be, well, external.

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  • \$\begingroup\$ (S)RAM may also be access by the DCode bus, if the vendor wired that in the bus matrix. \$\endgroup\$
    – Jeroen3
    Commented Dec 16, 2019 at 7:48

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