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I am having a QSPI Interface (operated in SDR mode) from this QSPI chip to MCU chip. QSPI lines :

  • QSPI CLK
  • QSPI CS
  • QSPI_IO0
  • QSPI_IO1
  • QSPI_IO2
  • QSPI_1O3
  • VSS
  • VDD

I am trying to validate the QSPI Setup time and Hold time parameters for the Data IO Lines with respect to the clock.

The data and clock lines are connected directly to the Micro with only a 47ohm 0603 resistor in series.

But if you check the Table 65 of the MCU datasheet (page 119), it is given as Setup time for incoming data and hold time for incoming data.

I am using 500MHz scope.

My doubts :

  1. If I probe the data lines, how will I know whether the data transitions in the IO Lines are incoming data or outgoing data?

  2. Apart from Setup time and Hold time validation, what are the other parameters I have to measure for validating QSPI lines from hardware perspective?

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  1. Look at the SPI command to see if it is a read or write.

  2. QSPI timing can not be verified by oscilloscope measurements. You must calculate the timing margins based on the worst case timing information in the MCU datasheet and the flash datasheet, the capacitive load, and the latency added by your PCB. There are lists of timing requirements in both the flash datasheet and the MCU datasheet. Your design must comply with all of them.

Oscilloscope measurement will only give you a "sanity check". You can check that the edges are in the vicinity of the expected typical timing based on your calculations.

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