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I've come across two different equivalent circuits for a non-ideal resistor and I'd like to understand which is correct. The first is:

enter image description here

and the second:

enter image description here

These are different equivalent circuits with different frequency responses. To show this I can take the parasitic values from the second link (C=0.3pF and L=1.5nH) and simulate both equivalent circuits with SPICE. For the simulation I'm using a voltage divider configuration with the top resistor non-ideal (arbitrary value of 1kOhm) and the bottom resistor ideal (also value of 1kOhm). The divider is driven by an AC voltage input of increasing frequency. Here's the first simulated circut:

enter image description here

And here's the second:

enter image description here

I measure the ratio of Vout to Vin (where Vout is the voltage measured across the ideal, bottom resistor). I've used the same frequency range. The plot for the first circuit is:

enter image description here

And the plot of the second:

enter image description here

There's nothing unexpected about this, since the parallel capacitor in the first circuit bypasses the resistor and inductor, whereas in the second, the capacitor is in series with the inductor.

It seems to me that the second circuit must be the correct one, since otherwise I don't see the point of ever using a speedup capacitor (the parasitic parallel capacitance basically acts as one). Is my intuition correct?

Note I've seen this answer which also seems to indicate the second circuit is correct. However, the linked to Vishay article uses the first circuit, although with added inductance due to the "external connection".

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The difference is the parasitics that each model considers.

The first model ignores lead inductance but accounts for something like inter-winding capacitance in wirewound resistors. Interwinding capacitance is identical capacitance you get in inductors between the adjacent coils sitting next to each other and lets sufficiently high frequencies completely bypass the bulk of the inductor.

The second model ignores interwinding capacitance but accounts for lead inductance.

So really, a better (but perhaps needless complex model for most uses) is a combination of the two.

It seems to me that the second circuit must be the correct one, since otherwise I don't see the point of ever using a speedup capacitor (the parasitic parallel capacitance basically acts as one). Is my intuition correct?

Why wouldn't you need still need one? Just because the parasitic capacitance is there doesn't mean it's large enough for your purposes.

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    \$\begingroup\$ ;) New rule. "No more lumped modeling anymore." We need to always provide "all the parasitics all the way down." Every parasitic has its own parasitics. And so on. We should never draw a schematic without all the parasitics and their parasitics and their parasitics.... Of course, it sacrifices readability. But at least it's more realistic! Hmm. I think we need to implement this down to the quantum behavior. All circuits should be built upward from quadrillions of quantum elements, and let the emergent phenomena develop out of simulation. I may need a better computer, though. \$\endgroup\$
    – jonk
    Dec 17 '19 at 22:47
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    \$\begingroup\$ @jonk I agree. No more made-up measurements like RMS or average either. We should only work with sets of instantaneous values. Will we need better brains too. \$\endgroup\$
    – DKNguyen
    Dec 17 '19 at 23:47
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    \$\begingroup\$ @jonk I realise you are being humorous, but if you model the real component by its transfer function (i.e. its real transfer function, not some idealized math formula from Control Systems 101) there is no need for an infinite regression of idealized parasitic components, or an over-complex diagram. \$\endgroup\$
    – alephzero
    Dec 18 '19 at 16:23
  • \$\begingroup\$ @alephzero Yeah. I was just being facetious. (I get like that once in a rare while.) \$\endgroup\$
    – jonk
    Dec 18 '19 at 18:35
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It's normally assumed that in practice, you'll only be using these components at frequencies sufficiently low so that $$ Z_\mathrm{L} \ll Z_\mathrm{R} \ll Z_\mathrm{C} $$ Under that condition, the current through the capacitor is always much weaker than through the resistor and the voltage across the inductor is much lower than across the resistor. Thus, to zeroth-order approximation, it doesn't matter whether the capacitor is in parallel with \$\mathrm{R} + \mathrm{L}\$ or with \$\mathrm{R}\$ alone, and likewise whether the inductor is in series with \$\mathrm{R}\:\|\:\mathrm{C}\$ or with \$\mathrm{R}\$ alone, and because you're only interested in the first-order impact of these components anyway, the total result is for practical concerns the same.

You can actually see that behaviour in your plots: only at the high-frequency end do the curves for both circuits diverge. How high that frequency is depends on the particular resistor; usually you'd pick those such that the impedance condition is obeyed.

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Quick Answer: According to Page 5-37 from Operation Manual of the 4195A Network/Spectrum analyzer equivalent circuit selection guide.

  • The First is for Resistors in general
  • The Second is best suited for High-Value Resistors

Long Answer:

I found a tutorial on equivalent circuits and simulation models from a Passives Handbook called : ABC of CLR from the European Passive Components Institute where they discuss the equivalent circuits which the HP4195A impedance analyzer uses to analyze and calculate the Device Under Test.

Page 5-37 from Operation Manual of the 4195A Network/Spectrum analyzer shows diferent equivalent circuits and type of DUT they are expecting for its analisis.

I'm attaching the table as it perhaps may aid in deciding which equivalent circuit suits which component when modeling them.

Table 5-8. Equivalent Circuit Model Selection Guide

This image is (C) HP / Agilent / Keysight , but since the product is obsolete and the manuals are freely available from the keysight website, I don't believe there should be a problem in reproducing it here

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