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I'm trying to understand why, on this circuit bit, they used pull-ups resistors between logic ICs of the 74LS and CD4000 families. Specifically I'm talking about resistor array RM1 and R1. All the ICs on this circuit are supplied by 5V. As far as I know, pull-ups are needed when you have open-collector/gate outputs/input, and not for TTL and CMOS devices, am I wrong?

enter image description here

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    \$\begingroup\$ General note: that might be an anti-glitch measure that brings the inputs to a defined state during device power-on or a brownout or similar situations, when the output stops being properly powered. \$\endgroup\$ – Marcus Müller Dec 18 '19 at 15:41
  • \$\begingroup\$ @MarcusMüller - Ditto: where ICs might be socketed or unpopulated. (And even if the final product has the IC soldered dev boards might have it socketed.) \$\endgroup\$ – TLW Dec 19 '19 at 7:04
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This is a case of interface between logic families (from LS-TTL -to- CMOS). Although both are powered from +5v supply, logic levels differ:

  • Logic low output for the 74LS93 is compatible with logic low input for CMOS 4002. No problem here.
  • Logic high output of 74LS93 is marginal compared to logic high input for CMOS 4002.

This is a matter of noise immunity: pull-up resistors ensure that a logic high is closer to Vcc of +5V rather than a \$V_{be}\$ lower than +5V.

Worst case \$V_{OH}\$ for 74LS93 is 2.7V
Admittedly, that's with Vcc at minimum 4.75V, and loaded with maximum current (0.4mA). When lightly loaded with high-impedance CMOS, far less static current flows.

Minimum acceptable \$V_{IH}\$ of 4002 is 3.5V
Clearly, the 74LS93 needs some extra help to pull up to 3.5V. 10k pull-up resistors do the job. Even so, at higher speeds, capacitance may slow the rising edge.

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  • \$\begingroup\$ How much does the 10k pullup affect the margin for logic low? \$\endgroup\$ – TLW Dec 19 '19 at 7:05
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    \$\begingroup\$ LS-TTL asserts logic low strongly: it can sink 8mA while remaining below 0.5V worst case...a 10k load only requires 0.5mA. On the CMOS input side, a logic low is any voltage below 1.4V. Do note that CMOS logic thresholds are highly dependent on Vcc (+5V), while LS-TTL thresholds are almost independent of Vcc. \$\endgroup\$ – glen_geek Dec 19 '19 at 13:54

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