My challenge at the moment is dissipating 60A of load current through an array of MOSFETs.

Here are my specs:


  • the rest of the circuit is some combination of MCU and 5V gate drivers
  • no switching of FETs after initial "on", then 60A sustained for 30 minutes without interruption
  • Likewise, 120A for 1 sec after initial "on"

Background Info: Schematic and Board of the FETs plus gate drive portions of the circuit are attached. You will see in the board that there is a separate polygon for "LOAD-". The bottom of the board has the same outline of a "LOAD-" polygon, and they are connected together by vias around the FETs and the solder pad, which is where the negative lead of the load wire is attached.

My question:

Are the calculations that I did below for PD (power dissipation), the equivalent junction temperature for 2x parallel, and the thermal resistances for 4x parallel all correct?

The reason I ask is because I ran this 60A test with a PCB that had 2x parallel, and within 15 seconds, one of the two FETs smoked, the load wire desoldered from the pad on the PCB, and the gate of that damaged FET melted to ground, so now there is a partial short. With all that, the rest of the circuit is still operational actually. So, curious where I failed to catch the schism between theoretical and practical.

Update 2020-1-3: Schematic was updated to reflect mods: QGATE changed to be on low side rather than high side, and values of RGL/RGPD changed to 1k/25k in order to bring rise time to 280us. Load test repeated with 30A instead of 60A. Test lasted for 5 minutes before FETs started smoking. Off button was pressed, and even though gate drive went to 0V, the FETs continued to conduct. Load wires desoldered from board. After test, gate signal shorted to ground but the rest of the circuit is still operational.


  1. Is this test indicative of the Spirito effect even though the FETs lasted for 5 minutes?
  2. If the root of the problem is not the rise time, then what is?

Thermal Calc: Thermal Calculation 2

Schematic: Schematic

Board: Board

Scope of Power FET Gate Drive: Scope

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    \$\begingroup\$ Doesn't look like your PD calculation is correct. Aren't you double counting current and MOSFET on resistance? PD=(Imax)^2*RDS(on), or PD=(Imax)*Vds(max)? \$\endgroup\$
    – SteveSh
    Dec 18, 2019 at 18:33
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    \$\begingroup\$ And what is your switching frequency and turn-on/turn-off times for the FET? In many cases the switching losses (dissipation) can be more than the DC power dissipation. \$\endgroup\$
    – SteveSh
    Dec 18, 2019 at 18:35
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    \$\begingroup\$ You should also specify when the 120A pulses can occur (only when everything is 'cold' or during this 60A?) and how frequent these pulses occur. \$\endgroup\$
    – Huisman
    Dec 18, 2019 at 18:36
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    \$\begingroup\$ The weak link is your thermal vias. Why are not using MCPCB? also coplanarity of surface is critical to Mae thermal grease thin without voids. \$\endgroup\$ Dec 18, 2019 at 19:19
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    \$\begingroup\$ "dissipating 60A of load current" - current isn't 'dissipated'. What are these FETs doing in the circuit, and what is the load? Can you show a schematic and board layout? \$\endgroup\$ Dec 18, 2019 at 19:24

4 Answers 4


What they told me about MOSFETs when I was at college

MOSFETs don't suffer from thermal runaway unlike BJTs

The lie they told me about MOSFETs when I was at college

MOSFETs don't suffer from thermal runaway unlike BJTs

The better picture:

The facts (thermal runaway can happen) are evident in almost every MOSFET data sheet and, the BUK9Y4R8-60E,115 is no different to the others: -

enter image description here

What you see above is a test that involves connecting a 10 volt (high current capability) supply between drain and source and measuring the current taken by the MOSFET under different conditions of gate voltage.

Look at the blue line and dot I added - this is known as the ZTC (zero temperature coefficient) gate voltage and it happens to be 3.1 volts. If you apply typically 3.1 volts there will be current taken by the drain but that current will not change as the device quickly warms up.

Now, if you applied 5 volts to the gate, as the device quickly warms up the drain current will go down i.e. it doesn't suffer from thermal runaway. However, if you apply a gate voltage that is typified by the red line and dot on the picture above you do get thermal runaway.

So, with 2.4 volts gate-source voltage and the MOSFET at ambient temperature, it will initially warm based on a power dissipation of 10 amps x 10 volts = 100 watts. The warming will be rapid and, as you can see, the temperature will rise and more power is dissipated causing the temperature rise to accelerate. At 175 °C the power is 40 amps x 10 volts = 400 watts.

But it won't stop there - the MOSFET will continue to warm (mainly in a single hot-spot) and, at around 600 °C, the MOSFET will catastrophically fail.

Hot-spots? Why hot-spots?

Modern MOSFETs (like the HEXFET) are constructed from quite literally tens of thousands of parallel MOSFETs and each one has its own characteristic, subtly different from the rest. So, if one happens to be more susceptible to thermal runaway compared to the others at a particular gate voltage, it will warm more quickly than the others and hog most of the drain current. This is a hot-spot.

However, if the gate voltage was above the ZTC, hot-spots wouldn't happen.

How quickly can this happen?

There are not many figures available but I estimate between 100 us and 10 ms. I've been there and seen it happen.


If you are using the MOSFET as a switch then use it as a switch and don't let the gate voltage dangle in the dangerous area for anything longer than 10 us (and even this might be a little too long).

What's wrong with your circuit

You have a 100 nF capacitor between gate and source and this is charged via a VN2110 MOSFET in series with a 4.7 kohm resistor (marked RGL). You hint that the gate receives 5 volts so I have to believe you and this means the unmarked supply that feeds the 4k7 is 5 volts and, that the VN2110 gate voltage activation signal is probably 7 or 8 volts minimum.

The RC time constant is 4700 x 100E-9 = 470 us. That means that 470 us after applying the initial activation signal, the voltage at the power MOSFET gate is around 3.15 volts (63% of 5 volts).

In other words, for a period of 470 us, the gate has been in the region that will cause thermal runaway in the MOSFET and dangerously so in my opinion.

But, it’s even worse when the MOSFETs are turned off because you have a 110 kohm resistor discharging C17 (100 nF) back to 0 volts and that time constant is 20 odd times longer.

But I'm using parallel MOSFETs

There is no benefit/mitigation in using parallel MOSFETs; they only load-share when the gate source voltage is above the ZTC point (just like the tens of thousands of parallel tiny FETs within each HEXFET).

Will a heatsink help?

No, the catastrophic event described above will be over in less than 10 ms and sometimes this may be as rapid as 100 us. It is highly likely that the MOSFET case will not even have started to warm to the touch by the time the "event" has rendered the MOSFET nonoperational.

Does this effect have a name?

This phenomenom is named "the Spirito effect" after Paulo Spirito who uncovered it and all the main MOSFET suppliers have white papers on it.

Another stack exchange answer that is relevant.

NASA report of a MOSFET failure in a power supply citing the Spirito effect.

  • \$\begingroup\$ Would it be reasonable to change RGL to 1kOhm and RGPD to 25kOhm, thereby decreasing the rise time to 100us and keep the gate drive at 5V? \$\endgroup\$ Jan 2, 2020 at 15:48
  • \$\begingroup\$ I would be aiming for rise and fall times that are less than 10 microseconds. @user2608147 \$\endgroup\$
    – Andy aka
    Jan 2, 2020 at 15:50
  • \$\begingroup\$ @user2608147 are we done with this question and answer? \$\endgroup\$
    – Andy aka
    Feb 15, 2020 at 18:03
  • \$\begingroup\$ I do not believe so. Although I understand the Spirito effect in theory, the behaviors that I am seeing during testing do not lead me to believe the Spirito effect is actually the problem here. I think it is more likely a heat dissipation issue. \$\endgroup\$ Feb 17, 2020 at 17:06

At 30A per FET you should have losses/heating of 30x30x0.0033. This is roughly 3watts. The FET shouldn't catch fire/melt even in free air like this...

Are you switching very fast? Even then it seems unlikely. Is your load actually shorted? Are your gates not being driven fully open/closed... If so the FETs will be operating with high resistance and will burn fast.

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    \$\begingroup\$ "The FET shouldn't catch fire/melt even in free air like this..." - how do you figure that? \$\endgroup\$ Dec 19, 2019 at 0:26
  • \$\begingroup\$ Without doing a more formal thermal analysis, it's hard to say for sure. But if you accept David Molony's 3 watt dissipation value, and given that the junction to thermal mounting base thermal resistance is 0.63K/W (from the data sheet), the junction temp rise is only 1.80 deg C. \$\endgroup\$
    – SteveSh
    Dec 19, 2019 at 1:18
  • \$\begingroup\$ Bruce, there are calculations, and then there is having a load of various size 3 phase inverter drives on your desk... \$\endgroup\$ Dec 19, 2019 at 8:47
  • \$\begingroup\$ A few other reference points... 1) i have a to220reg dropping from 15v to 3.3v with about 250mA. It gets hot, but it's nowhere near burning up. That's 3watts. 2) my soldering iron takes much longer than 15 seconds to get to solder melting temperature. That's got a 40w element and the tip is bigger but not 10x the mass or surface area... I'm not saying this is a good idea, just that it's very unlikely that the cause of his FET burning in 15 seconds was the amount of heat sinking. Something else went wrong. \$\endgroup\$ Dec 19, 2019 at 9:03
  • \$\begingroup\$ In light of the PCB and schematic being posted, it seems likely the issue is (as Andy says) that you're not driving the MOSFET on properly... By Andy's calc half a millisecond... During which you dissipate several hundred watts, which will quickly trash the FET... Get a proper gate drive. Did you retest? If not try without the cap and with lower value resistors... \$\endgroup\$ Dec 31, 2019 at 18:54

VGS = 5 V; ID = 25 A; Tj = 25 °C; Rds of 0.0048 ohm max, need to design for worst case.

P = I^2 * R @ 30A, = 30*30*.0048 = 4.3W @ 60A, P = 60*60*.0048 = 17.28W - for a whole second. I would think you'd need a decent heat sink for that.

What does C17 do? I would think it would impact the rise & fall times of the gate signal.

Also, RGL, QGate, RGPD, and whatever the thing is hanging off the gate will impact high the gate signal goes, which will impact Rds. A higher gate signal is better. If you can get it closer to 10V, that would be better.

  • \$\begingroup\$ C17 is a gate noise suppression cap. I noticed that with an inductive load like in our application, the gate voltage will fluctuate, resulting in some damaging effects on the 5V rail and MCU (this was fixed by adding a gate drive FET QGATE). I do not have additional room for another buck converter, to get 10V, without a major redesign. \$\endgroup\$ Jan 3, 2020 at 23:44

The answer is: not enough heat-sinking.

CrossRoads had the closest answer. I believe Andy aka had a super insightful answer, but the delay in switching didn't cause my circuit to break down. David Molony was on to it as well, but there actually is a heck ton of power being pumped through those MOSFETs and nowhere for it to dissipate to.

The new version of the PCBs I designed had the following modifications:

  • Separate PCB for MOSFETs (daughter board)
  • 4 MOSFETs in parallel instead of 2
  • Larger copper area for LOAD-
  • 2 oz. copper
  • Daughter board is aluminum without vias

I will continue to test and see if I can optimize this back down to 2 MOSFETs and 1 oz. copper. Also, I have a different variation of the daughter board that is FR4 with vias, therefore lower in cost/shipping time. But, as far as this post is concerned problem solved.


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