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A PCIe expander allows to have more PCIe slots from a single one available in the computer.

How exactly is the performance affected? Are the output slots in parallel, and therefore the bandwidth decreases by a factor of 3?

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    \$\begingroup\$ The picture is of a PCI backplane. Which one do you mean, PCI or PCIe? \$\endgroup\$
    – Justme
    Dec 18 '19 at 18:25
  • \$\begingroup\$ Sorry I just googled a picture of the form factor I wanted to show. I am using PCIe. Is there a difference between PCI or PCIe for this application? \$\endgroup\$ Dec 18 '19 at 18:30
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    \$\begingroup\$ @SuperCiocia yes. PCI is a shared bus, whereas PCIe is a point-to-point architecture with the option of lane aggregation. So, basically, PCI and PCIe couldn't be more different! \$\endgroup\$ Dec 18 '19 at 18:32
  • \$\begingroup\$ Get an oscilloscope and see what the performance is by looking at the eye diagram \$\endgroup\$
    – Voltage Spike
    Dec 22 '19 at 5:54
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There's different things that can be called expanders:

  1. Lane bifurcators
  2. PCIe switch-based backplanes

Lane bifurcators

A PCIe socket can have more than 1 PCIe lane – for example, x4 and x16 lane slots are pretty common. If the root complex and all PCIe switches in between support it, these lanes can either be used for only one link, giving more bandwidth, or be split among different PCIe devices.

If that is supported, then a basically passive card could be used to e.g. connect four x1 sockets to a x4 socket. Again, this is a special case and needs support from the hardware. That technique is called "lane bifurcation".

Obviously, that means the overall bandwidth is split according to the number of lanes that the end devices get.

Full switch-based backplane

PCIe is a point-to-point link system.

Hence, just like in Ethernet, you can have switches that add more links to a single link. Of course, the devices sharing that link can not magically get a higher sum bandwidth than that original link offered, but the bandwidth isn't statically alotted – just as in ethernet, each device will get as much bandwidth as it wants until the bottleneck gets congested.

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  • \$\begingroup\$ What's the difference between ethernet & and PCIe, and a shared bus then? Doesn't a shared bus also give as much bandwith to its elements until a bottleneck happens? \$\endgroup\$ Dec 18 '19 at 22:57
  • \$\begingroup\$ Also, how do I know whether or not I am going to hit the bandwidth limit? Can I know the max bandwidth of my computer (on that PCIe slot) and the bandwidth needed by my device? \$\endgroup\$ Dec 18 '19 at 22:58
  • \$\begingroup\$ @SuperCiocia a PCIe lane has a maximum number of bits per second, which depends on the PCIe generation. Whether or not your computer is up to dealing with that continuously on all lanes is up to what your computer is, and what it does with the data. What your device needs depends on the device. Your not telling us any of that :) \$\endgroup\$ Dec 19 '19 at 12:34

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