As oldfart correctly points out: This answer applies to verilog meant to actually define hardware only; for simulation models, see his answer!
For example, if the input is a 1ns pulse, then I want the output to be 2ns pulse
That's not among the abilities of verilog, as far as I can tell; since this is not a logical or clocked thing that you want, it's impossible to represent it in verilog.
However, let's rephrase:
If the input is a pulse that lasts for N clock cycles, then I want the output to be 2N clock cycles long.
Then it's really just counters: one increasing a "must still be emitted count" by one per clock cycle as long as the input is high. You'd add minimal logic: The output is high as long as the input is high OR the counter > 0. Also, for as long as the input is low, and counter > 0, decrease counter by 1.
Done! All you need is clock that is at least as fast as the shortest pulse you want to deal with. But that's kind of a given, since this really is digital logic, and not analog circuitry.