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I have another question regarding some VHDL. I am trying to create a pulse of 5 ms output (in my code a_full), however, I am struggling to find any information on how to generate this, basically I want a full pulse of 5 ms when the count reaches 12 and for that to reset the count.

Can anyone please point me in the right direction?

I have added my code for reference.

-- Library Decleration 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


--entity declaration
entity egg_sorter is
    port (  Reset       : in std_logic;
        Egg_Size    : in integer range 0 to 7;
        Egg_available   : in std_logic;
        A_Count     : out integer range 0 to 12;
        A_Full      : out bit;
        b_Count     : out integer range 0 to 12;
        b_Full      : out bit;
        c_Count     : out integer range 0 to 6;
        c_Full      : out bit;
        d_Count     : out integer range 0 to 6;
        d_Full      : out bit
        );
    

end entity;

-- architecture 
architecture behavioral of egg_sorter is

-- signal declerations due to being outputs and VHDL not being able to read outputs
signal A_Count_Value : integer range 0 to 12;
signal A_Full_S : bit;
signal b_Count_Value : integer range 0 to 12;
signal b_Full_S : bit;
signal c_Count_Value : integer range 0 to 6;
signal c_Full_S : bit;
signal d_Count_Value : integer range 0 to 6;
signal d_Full_S : bit;

begin 
    -- this is the count process for size A eggs

Process (Reset, Egg_Size, Egg_available)
    Begin
        if reset <= '1' then
         b_count_value <= 0;
        
        end if;
    

            case egg_size is
                when  0 to 2 =>
                    if rising_edge(egg_available) then

                        if a_count_value < 12 then
                            A_Count_value <= A_Count_value + 1;
                        elsif a_count_value <= 12 then
                            a_full_s <= '1';
                            a_count_value <= 0;
                        
                        end if;
    
                    
                    else a_count_value <= a_count_value;
        
                    end if;
                    b_count_value <= b_count_value;
                    c_count_value <= c_count_value;
                    d_count_value <= d_count_value;


                when  3 | 4 =>
                    if rising_edge(egg_available) then
                        if b_count_value < 12 then
                            b_Count_value <= b_Count_value + 1;
    
                        elsif b_count_value <= 12 then
                            b_full_s <= '1';

                        end if;
                    else b_count_value <= b_count_value;

                    end if;

                    a_count_value <= a_count_value;
                    c_count_value <= c_count_value;
                    d_count_value <= d_count_value;

                when 5 | 6 =>   
                    if rising_edge(egg_available) then
                        if c_count_value < 6 then
                            c_Count_value <= c_Count_value + 1;
    
                        elsif c_count_value <= 6 then
                            c_full_s <= '1';

                        end if;
                    else c_count_value <= c_count_value;

                    end if;

                    a_count_value <= a_count_value;
                    b_count_value <= b_count_value;
                    d_count_value <= d_count_value;

                
                when 7 => 
                    if rising_edge(egg_available) then
                        if d_count_value < 6 then
                            d_Count_value <= d_Count_value + 1;
    
                        elsif d_count_value <= 6 then
                            d_full_s <= '1';

                        end if;
                    else d_count_value <= d_count_value;

                    end if;

                    a_count_value <= a_count_value;
                    b_count_value <= b_count_value;
                    c_count_value <= c_count_value;
    
            end case;

    end process;
    

A_Count <= A_Count_Value; -- this puts my signal value to my output
a_full <= a_full_s;

b_Count <= b_Count_Value; -- this puts my signal value to my output
b_full <= b_full_s;

c_Count <= c_Count_Value; -- this puts my signal value to my output
c_full <= c_full_s;

d_Count <= d_Count_Value; -- this puts my signal value to my output
d_full <= d_full_s;

end behavioral;
```
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  • 1
    \$\begingroup\$ howcome you don't have a clock? \$\endgroup\$
    – stanri
    Jan 19, 2020 at 16:44

1 Answer 1

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I have not tried this yet, but how about something like:

d_full_s <= '1';
wait for 5 ms; 
d_full_s <= '0';

You may also need to set all of the strobes to zero early near the beginning as part of your reset, to prevent erroneous values.

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  • 4
    \$\begingroup\$ As Adam Bromby is a new member it's advisable to update your answer to indicate that it only works for simulations. Additionaly you could show a synthesizable solution with a counter. \$\endgroup\$
    – Kitana
    Dec 28, 2019 at 19:23

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