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schematic

simulate this circuit – Schematic created using CircuitLab

Suppose we have a NMOS transistor, with and ideal current source (I_S) in its source. The drain is connected to V_DD, and the gate is just floating. It certainly cannot be cut-off since we have forced a current in its source, but is it triode or saturated? What if we change the MOS transistor to a BJT?

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    \$\begingroup\$ In general, for any significant current, the ending state is what senior engineers call "burnt up". The part would go into breakdown (avalanche in the case of the BJT; I'm not sure what FETs do in that circumstance). If you did this in the real world with a FET the results would be extremely unpredictable, because the open-circuit source could float to nearly any voltage. \$\endgroup\$ – TimWescott Dec 22 '19 at 3:22
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    \$\begingroup\$ The gate looks like a capacitor. This means that \$V_{GS}\$ is more or less arbitrary, and in the real world will be strongly influenced by external forces. In a simulated environment (which you can try for yourself, with the simulation environment that @KingDuken mentioned), the rising drain voltage might pull the gate voltage up enough for it to conduct enough for the transistor to naturally pass enough current to avoid voltage breakdown -- or it might not. In a real environment, with who-knows-what parasitic resistances, all bets are off. \$\endgroup\$ – TimWescott Dec 22 '19 at 3:35
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    \$\begingroup\$ "since we have forced a current in its source" - No, you haven't. Connecting a current source to an open circuit does not "force" anything. If the potential difference between the gate and source is not enough to enhance the channel, there will be no current. \$\endgroup\$ – AnalogKid Dec 22 '19 at 4:51
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    \$\begingroup\$ Deep-ending on how idealised the FET is the source will be at 10 or 1000 or 1,000,000 or .... volts . | You cannot play "apply random undefined unspecified out of bounds" conditions and expect other than random undefined unspecified out of bounds results. \$\endgroup\$ – Russell McMahon Dec 22 '19 at 4:59
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    \$\begingroup\$ what state depends on Vgs, which is indeterminate. \$\endgroup\$ – Jasen Dec 22 '19 at 9:26
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Your schematic shows a P-channel MOSFET, but operation is the same for NMOS.

When the Gate is 'floating' it will have a voltage determined by whatever charge was stored on it before being put in the circuit. So it might be cut off or it not might not be, depending on its previous history.

An 'ideal' MOSFET has no leakage and no breakdown voltage. If your circuit had only 'ideal' components and VGS was zero, then the ideal FET would be perfectly cut off and the ideal current would produce infinite voltage across it (which is impossible of course, but when an unstoppable current meets infinite resistance...).

But real FETs do have these 'flaws', so in practice it would at least pass the constant current corresponding to the leakage current at the voltage required to produce it. If the constant current was higher than the leakage current at normal operating voltage then VDS would increase until it reached the avalanche breakdown region, where the FET would act like a Zener.

If the floating Gate had sufficient charge to turn the FET on enough to keep VDS below the breakdown voltage then it would either be in the linear or saturated region, depending on VDS and ID.

(Graph from Toshiba app note 20810726: Selecting MOSFETs and Consideration for Circuit Design) enter image description here

Bipolar transistors behave similarly, except the Base needs continuous current to keep the transistor turned on. So if the Base was open circuit the transistor would stay cut off until reaching its breakdown voltage. The curve trace below was taken from a PNP transistor rated for a maximum VCEO of -25V. It shows a smooth breakdown transition at ~-30V, drawing ~6mA at -35V. (the sharp drop at the bottom left of the curve is caused by reverse Base-Emitter breakdown at ~+6V).

Many bipolar transistors have a negative resistance characteristic in the breakdown region, where as current increases the voltage drops to a lower value called VCEO(sus) (sustaining voltage). This shows up on the curve tracer as an instability at the breakdown transition.

enter image description here

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