Your schematic shows a P-channel MOSFET, but operation is the same for NMOS.
When the Gate is 'floating' it will have a voltage determined by whatever charge was stored on it before being put in the circuit. So it might be cut off or it not might not be, depending on its previous history.
An 'ideal' MOSFET has no leakage and no breakdown voltage. If your circuit had only 'ideal' components and VGS was zero, then the ideal FET would be perfectly cut off and the ideal current would produce infinite voltage across it (which is impossible of course, but when an unstoppable current meets infinite resistance...).
But real FETs do have these 'flaws', so in practice it would at least pass the constant current corresponding to the leakage current at the voltage required to produce it. If the constant current was higher than the leakage current at normal operating voltage then VDS would increase until it reached the avalanche breakdown region, where the FET would act like a Zener.
If the floating Gate had sufficient charge to turn the FET on enough to keep VDS below the breakdown voltage then it would either be in the linear or saturated region, depending on VDS and ID.
(Graph from Toshiba app note 20810726: Selecting MOSFETs and Consideration for Circuit Design)
Bipolar transistors behave similarly, except the Base needs continuous current to keep the transistor turned on. So if the Base was open circuit the transistor would stay cut off until reaching its breakdown voltage. The curve trace below was taken from a PNP transistor rated for a maximum VCEO of -25V. It shows a smooth breakdown transition at ~-30V, drawing ~6mA at -35V. (the sharp drop at the bottom left of the curve is caused by reverse Base-Emitter breakdown at ~+6V).
Many bipolar transistors have a negative resistance characteristic in the breakdown region, where as current increases the voltage drops to a lower value called VCEO(sus) (sustaining voltage). This shows up on the curve tracer as an instability at the breakdown transition.