Im new to electronics. In fact, I'm a computer scientist looking into embedded systems. I am going through Vol. 1 of Jonathan Valvano's book on embedded systems and got stuck when i read on Gated D Latches:
See the truth table where W is the enable input:
The fall and rise of a clock usually refers to the Rising Edge and the Falling Edge. And that's just what it sounds like. It's the short period of time when the clock goes from Digital LOW to Digital HIGH and vice versa.
What does it mean when an input falls? He says that: "the last D input is remembered or latched when the enable input falls"???
The way a D-Latch works is as such: when the enable bit (in this case W) is set to HIGH, Q = D. And Q will always equal D as long as W is HIGH. But when the enable bit (W) is LOW, Q no longer equals D and the state of Q will not change until W is set HIGH again. During this time, Q = the last state D was in right before W = LOW.
In the image above, our enable bit is represented as E instead of W.
When the input goes from high "1" to low "0" that's falling.
Another term for this even is a "fallling edge" on the input.
in the table the enable input is labeled "W"
The table says that when "W" is high "D" is passed through to "Q" but and when "W" goes low this state is remembered. while "W" is low "Q" is locked and "D" is ignored.
Rise is the opposite of fall changing from low to high "0" to "1"
