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I have this truth table:

enter image description here

Which gives this SOP

y = A'B'C + A'BC' + AB'C' + ABC

I tried to use a MUX with 2 selects and 4 inputs and I got this (using A and B as the selectors):

enter image description here

I'm pretty sure it's correct because when I light up A, B and C according to the truth table I get the right value for Y but I just want to make sure.

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    \$\begingroup\$ First of all, have you checked the datasheet for this chip? Secondly, it's hard to understand what you're trying to do. A MUX device is supposed to stream a serial output of bits depending on the data selection you assign. I really don't think you're using this MUX for its intended purpose. \$\endgroup\$
    – user103380
    Dec 22, 2019 at 17:52
  • \$\begingroup\$ @KingDuken I have. It's a multiplexer. D0-D7 are inputs, A,B and C are selector, with A being the least significant one. Y and W are outputs, S is enable. What I am trying to do is use a mux to implement that SOP. Or at least that's what my professor wants us to do. \$\endgroup\$ Dec 22, 2019 at 17:55
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    \$\begingroup\$ @SilenceOnTheWire Well, your circuit does what you are supposed to make it do. So, that's good! \$\endgroup\$
    – jonk
    Dec 22, 2019 at 20:16
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    \$\begingroup\$ @SilenceOnTheWire Also looks like you are using Neemann's Digital. Good!! That's the best available for things like this, right now. You should add in test vectors to your schematic. That way, you have automatic verification. \$\endgroup\$
    – jonk
    Dec 22, 2019 at 20:29
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    \$\begingroup\$ @SilenceOnTheWire This screen capture shows what I mean. Digital makes it very easy to add this feature. All eight of those text vector lines could also be replaced with just one line: "repeat(8) bits(3,n) (((n>>2)+((n>>1)&1)+(n&1))&1)". \$\endgroup\$
    – jonk
    Dec 22, 2019 at 20:42

3 Answers 3

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y = A'B'C + A'BC' + AB'C' + ABC

Given enter image description here to implement with 8:1 mux. with 3 address inputs.

y=1 ABC
    001 = d1 =>"1"
    010 = d2 =>"1" 
    100 = d4 =>"1"
    111 = d7 =>"1"
y = 0 for d0=d3=d5=d6="0"  
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That looks like a correct implementation of the 3-bit parity function to me.

you've used an 8:1 mux instead of 4:1, but as you're only using 2 of the address lines I guess that's ok.

As jstola says writing it in logic diagrams instead of wiring may be preferred.

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This is not an answer.

Please get accustomed to using logic symbols instead of using a wiring diagram as you have in your question.

It will make your life easier when the circuits get more complicated.

Here is a random example from the web.

enter image description here

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