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A mistake was made when designing a set of mother and daughter PCBs, resulting the daughter board to have its LVDS pairs at ~100Ω differential impedance, while the motherboard ~90Ω. The receiver, which is on the motherboard, is a standard LVDS receiver, with 100Ω termination resistors. Those pairs connect via a dedicated FFC cable. The designs are already at the manufacturer and cancelling the order will cost a lot. What are the chances that the communication will survive this mismatch? The clock of the data transfer is between 300-400 MHz.

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  • \$\begingroup\$ Cables are barely within those tolerances, but you can simulate that in Falstad in about 5 minutes \$\endgroup\$ Dec 22, 2019 at 23:06
  • \$\begingroup\$ take 2 tinyurl.com/rbev3wx tweak model as desired . geometry is everything \$\endgroup\$ Dec 22, 2019 at 23:59

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There's a neat little return loss and mismatch calculator that I like to use for these situations. 100R into 90R gives a reflection loss coefficient of 0.0526, meaning you're reflecting 5.26% of your signal back.

If your receiver can reject that level of noise, and you can deal with potentially 11% higher peak voltages in your waveform (due to standing waves), you should be ok.

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