I tried simulating both:

Falling edge triggered one

Regular clocked JK flip flop

I think there is something wrong with them because when both inputs are high they look like they are having a seizure rather than toggling.

I thought I understood it, I've tinkered with it, I've looked at the scopes but at this point I am a bit lost.


2 Answers 2


You can only make latches this way and bad ones too that oscillate with negative feedback. Notice the blur of oscillations. when both JK =1.

enter image description here

True Flip Flops MUST HAVE 2 latches to make the output edge triggered so that the 2nd stage input conditions cannot change on the clock edge.
enter image description here They are actually implemented in CMOS Transmission gates as well.

  • \$\begingroup\$ But am I not suppose to use something like this when I want to make a falling edge triggered flip flop? sub.allaboutcircuits.com/images/04191.png \$\endgroup\$ Dec 24, 2019 at 2:43
  • \$\begingroup\$ What part of that is an invalid FF do you misunderstand? \$\endgroup\$ Dec 24, 2019 at 4:24
  • \$\begingroup\$ I believe you. I'm just surprised because I've seen my professor do this and accept projects that were done like this. \$\endgroup\$ Dec 24, 2019 at 5:21

The first simulation (falling edge triggered ff) works pretty good and is the correct way to go for this type of ff. This type of ff must be clocked with a very short clock pulse as you are doing. The clock pulse must be removed before the feedback gets back to the inputs to avoid instability. You could try removing two of those not gates to shorten the clock pulse even further in order to try and remove that last bit of instability that is occasionally occurring.

  • \$\begingroup\$ If the flip-flop requires a "very short clock pulse" then it is not "falling edge triggered", it is an active-high level-sensitive latch. \$\endgroup\$ Dec 27, 2019 at 16:01
  • \$\begingroup\$ It is not a latch. The flip flop's outputs respond shortly after the clock goes negative for all four combinations of the J&K inputs (00 01 10 11). It's just that in the last mode, toggle mode (J=K=1), the outputs will oscillate if the clock pulse lasts longer than the time taken for the outputs to respond to the inputs and be fed back. Making the clock pulse very short to avoid this oscillating instability in toggle mode (J=K=1) is a standard technique for this form of edge triggered flipflop. \$\endgroup\$
    – James
    Dec 28, 2019 at 10:19

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