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Lets say I have a linear circuit with some input and output voltages. Assume this is a block with inputs/outputs. When I connect input of another block to the output of my first block, I observe that my first output will change but I don't want it to change or I want to be able to foresee this change and interfere beforehand to sustain my second block with that original output signal.
What can I do about it?
Do you mean "change level slightly" or "change state"/ change excessively compared to expectation.
The first is a natural consequence of applying ANY load to ANY source - how much the change is depends on source and load impedances.
Simplistically Vout = Voc x Zload / (Zsource + Zload).
If this is unacceptable then feedback will allow "zero" change or (as Andy says) a buffer with lower Zsource can be used.
In logic systems these are designed to allow a certain number of loads to be connected without taking performance outside specification. The number of standard loads that can be accommodated is termed "fanout".
In analog systems it's up to you to design to suit your need.
If a load causes a source to change state or to change "too much" then "you are doing something wrong" - the circuit needs to be properly designed.
Lets say I have a linear circuit with some input and output voltages. Assume this is a block with inputs/outputs.
You need to tell us whether this is passive or active. (Active means it has powered amplification components.)
When I connect input of another block to the output of my first block, I observe that my first output will change but I don't want it to change or I want to be able to foresee this change and interfere beforehand to sustain my second block with that original output signal.
You have a couple of options here.
All sources have resistance even the grid. Voltage sources are practically defined by zero Ohms voltage source symbol and a series resistance, Rs.
This is also true for passive switches, inductors , L+ DCR , capacitors, C+ ESR and is normally measured at Dc for inductors and some std. f for capacitors.
This is also true for batteries Vbat, ESR which are actually like true voltage sources with a massive supercaps, >10kF, in series for charging up the voltage about 10%.
The same is true for current sources defined by high impedance controlled current and some parallel load resistance like common emitter transistors with Rc.
The same is true for Op Amps which can reduce the output error with negative feedback and thus reduce the output impedance of the internal series resistor by the same amount until the current limit is reached.
In general this load reduction of voltage is commonly specified in voltage regulators as Load Regulation Error (%) which is always due to the impedance ratio of the load to the Load + source (%).
In RF amplifiers low impedance is often necessary and both voltage and current are important so we always deal in power (Watts). Also since maximum power is often important between stages, the impedance must be matched. This is true for 50 Ohm system but it also means the load loss is 50% in power but that is still the max. power transfer condition.
We would not want this load regulation error for a DC power supply so they are often specified <= 2% and thus by V/Imax * % error we can estimate the source impedance. Yet for a PV Solar Array where power = P= V*I if we load it down we must know its current source impedance R=Voc/Isc and always load with the same impedance, R in order to obtain this power which often occurs at <82% Voc.
For voltage amplifiers we need more current and a lower output impedance.
For active switches like FETs we need lower RdsOn and for Bipolar Junction transistors (BJT) , we need lower Rce = Vce/Ic when saturated.
p.s. Season's greeting from Toronto
