In the SoCs that I am working on, memory rail has to be powered up first and then the logic rail. And memory rail is expected to be higher in voltage than logic rail at any point in time. Could you explain me the possible reasoning behind it?There are transistors that are reversed biased with these voltage rails and if the higher voltage rail is turned on later, they get forward biased leaking a lot. But, i need a little more explanation on possible functions of such transistors - may be 1 or 2 examples would be great. I had heard that level shifters go only one way that puts a restriction on power on sequence. But I did not understand how.
Normally SoC's are all CMOS and all CMOS devices cannot have any low impedance input voltage exceeding a diode voltage outside either supply rail, Vdd,Vss, otherwise an inherent substrate PNPN = "SCR effect" causes latchup and shoot-through or short circuit when power is applied. You can search for this effect for more details.
Normally 0.2V is permitted in Absolute Maximums and inputs are protected with Schottky diodes and 10 k series current limiting Rs on inputs.
But the effect is in the substrate between power rails and the input or output is a trigger that must be avoided by a controlled power sequencing.