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In the SoCs that I am working on, the memory rail has to be powered up first and then the logic rail, and memory rail is expected to be higher in voltage than the logic rail at any point in time. Could you explain the possible reasoning behind it?

There are transistors that are reversed-biased with these voltage rails and if the higher voltage rail is turned on later, they get forward biased, leaking a lot. I need a little more explanation on possible functions of such transistor, one or two examples would be great. I had heard that level shifters go only one way which puts a restriction on the power-on sequence, but I don't understand how.

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  • \$\begingroup\$ General comment that MAY apply: Some devices will enter a latch-on stage if reverse biased. In such cases power sequencing may matter. In older logic I/O pins taken outside supply rails could sometimes form parasitic SCR's that not only latched on but would in some cases destroy the IC by overheating. Modern ICs usually are designed to prevent such parasitic structures being formed. \$\endgroup\$
    – Russell McMahon
    Dec 25, 2019 at 12:04
  • \$\begingroup\$ Memory has to be up and capable of running before any cpu action or it might start executing garbage and get in a pickle. \$\endgroup\$
    – Andy aka
    Dec 25, 2019 at 12:12
  • \$\begingroup\$ Hello Andy, but the reset to SoC is deasserted only after all the required rails are powered. So, CPU starts executing only after CPU and memory are powered and then reset is de asserted. \$\endgroup\$ Dec 25, 2019 at 12:27
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    \$\begingroup\$ Only the manufacturer may be able to tell why some power island needs to be up before others. \$\endgroup\$
    – Justme
    Dec 25, 2019 at 12:57
  • \$\begingroup\$ Many years ago, I was using a Virtex II (I said it was a while back...) where it had 4 power rails. The rails had to be sequences such that the lowest of any 2 voltages could not exceed the higher voltage rail at any point. I haven't seen anything quite so stringent recently, but I have seen a situation in the last 4 years where the memory controller might not operate properly unless it was the first rail asserted. \$\endgroup\$ Dec 25, 2019 at 14:07

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Normally SoC's are all CMOS and all CMOS devices cannot have any low impedance input voltage exceeding a diode voltage outside either supply rail, Vdd,Vss, otherwise an inherent substrate PNPN = "SCR effect" causes latchup and shoot-through or short circuit when power is applied. You can search for this effect for more details.

Normally 0.2V is permitted in Absolute Maximums and inputs are protected with Schottky diodes and 10 k series current limiting Rs on inputs.

But the effect is in the substrate between power rails and the input or output is a trigger that must be avoided by a controlled power sequencing.

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