Frequency Domain Analysis with Transistors

Question

I have some doubts about how some circuits with transistors are described in electronics textbooks. Let's see an example (taken from Thomas H.Lee, The Design of CMOS Radio-Frequency Circuits).

This books (and all other books I have read about circuits with transistors) uses a convention in which signals in time domain are indicated with small letters. So for instance iout = iout(t).

Let's consider this example with a Small Signal Mosfet model with parasitic capacitances:

The book considers the situation in which a current source iin is put at the input of the Mosfet, and tries to evaluate the current gain. The result of the analysis is this one:

You may see there is the variable ω, which is due to the presence of the capacitances. My question is: how can be this analysis correct? It is a time domain analysis, so it is not correct to say that the voltage drop on a capacitance is 1/jωC * current: we should use integrals.

I think the previous relationship is true only if we indicate with \$i_d\$ and \$i_{in}\$ the fourier transforms of the drain current and input current. But they have been defined as time domain signals.

The book goes on and uses also equations like that of the drain current of a MOSFET in saturation (\$i_d = k(v {gs} - v_t)^2)\$ and always in time domain. How can this analysis be correct? I'll replace all these signals with their Fourier transform: is it true?

Answer 1

Yes, the book is playing a bit fast and loose with conventions -- but because they're conventions and not hard-and-fast rules, you need to just roll with it and try to understand the author's intent.

That expression is calculated in the Laplace or Fourier domain, to find the response of the circuit to sinusoidal signals in steady-state. So by that measure, and by "normal" convention, the author should have used \$I_d\$, \$I_{in}\$, etc. However, the notation above is practically a convention in itself for this sort of circuit analysis so -- roll with it.

Answer 2

I think the analysis is wrong.

I propose the AC current gain =1.

It seems reasonable to me that the current is entirely due to the input and load capacitance and so the Current Gain ratio is not a function of frequency, nor gm until those impedances approach the RdsOn. The analysis can be done in both time or frequency domain. I chose the time domain as follows.

To simulate this , I chose a true current source load with an input generator with DC bias just above threshold Vt using a 20mVpp triangle voltage waveform.

• With no Miller Cap. Cdg the gate current is a square wave = 0.5uApp (not shown) which is negligible compared to the 1mApp gate current below. This practically means all the AC drain current here is due to the Miller Capacitance.

  • Using a current source to eliminate loading gives the maximum voltage gain.

  

The voltage gain is 14.4Vpp / 0.02Vpp= 720

The current gain is ~ 1 = (10.593-9.422)mA / (593.765 + 578.468)uA = 0.99895 Almost all of the gate current is due to the Miller Capacitance which is the same as the drain load current with a current source.

So we expect the current gain is only unity and independent of frequency if 1/ ωCm >> RdsOn

My Simulation agrees.

Then when you replace the current source load with a fixed resistor, the current gain becomes a product of the voltage gain and AC load current.

Using Vpp probes shown below across current sense resistors.

So what current gain do you see now?