tl;dr because there are real-world issues that prevent us from setting I/O standards and other specifications willy-nilly. If EE were so simple a lot of us wouldn't have jobs or thesis projects.
To start, there are tons of practical reasons why we don't just increase I/O voltage. It's not as simple as some guy crossing out 3.3v on a piece of paper and writing 12v instead. Modern CMOS processes for processors are designed to create thin gate oxides for fast, low-voltage devices. The processing steps needed to grow a thick gate oxide would be both costly and adversely affect performance and yield. The nice thing about a lot of cheap ICs is that they have a simple process--a 3v3 chip might have all gate oxides grown to withstand 3.3v+safety factor. You've now introduced multiple new masks (plus photoresist and etching steps), perhaps doubling or tripling the price of the chip.
Likewise, power dissipation for high-speed circuitry would be an issue. Especially for fast signals, high voltage swings imply high power dissipation (on the order of voltage squared) due to capacitances and series impedances. Additionally, if you must maintain your core at 3.3v to remain within a power/thermal budget, you'll need to add level shifting, which itself generates additional heat, consumes additional power, and causes users to incur additional costs.
Your thresholds are also fairly arbitrary--a sharp 6V threshold requires a voltage comparator, which leads to its own instability problems in case of certain feedback structures that could very well arise on a floating pin. For a reasonable I/O buffer, the threshold is going to be a reflection of the gate threshold voltages of the transistors in the buffer, which ties back to our manufacturing limitations. You run into the same shoot-through problems, but they're worse now since the region where both FETs are on is wider thanks to the higher rails, and the supply voltage is higher leading to yet more power dissipation. You've made the issue worse rather than better.
Now, with all of that said, simply making I/O thresholds higher isn't going to fix the issue of floating signals. Given the amazingly high resistance of the gate oxide, a floating pin can easily reach 6V--especially given that there's a >6V rail nearby!
When all of this is said and done, we've delayed chip production by a year while we develop fabrication processes and establish contracts to do mixed-voltage systems with both high-performance cores at 1v2 and 12V I/Os. We've pushed our power budget up, meaning that we must buy more expensive heatsinks and fans, as well as larger batteries and power supplies, and we also haven't reliably fixed the issue.
Or, you could buy a tape/reel of 10000 pullup/pulldown resistors for $10 on DigiKey, or for less in Shenzhen. More likely than not, your PCB manufacturing partner already has some standard pullup/pulldown resistor on hand, loaded in their pick-and-place machines, and ready to be placed. Or, your chip might already include pullups/pulldowns, since those can be fabricated fairly easily on some processes using weak MOSFETs.