Logical reading (1 or 0) of a micro-controller input GPIO pin may float if it is neither connected to VCC nor GND; someone said it is because of surrounding RF interference.

When a floating GPIO input pin voltage is affected by RF interference that makes it fall in the undefined logical range (i.e. 0.8V - 2.2V for Raspberry Pi), it can cause the logical value of a floating pin to change.

I wonder if this problem could be solved by how a microcontroller is designed. i.e. Enlarge the logical voltage range, say <6V for low >6V for high. Since interference may seldom reach such high level voltage.

  • 9
    \$\begingroup\$ No matter what the switching threshold is, if there is no driver on the input, then it will need a pullup or pulldown or something similar to force it to a known and valid level. In general, if RF noise is a problem, a capacitor is a better fix than a pullup or pulldown. But the pullup/pulldown may still be needed to insure the input is in the correct state. \$\endgroup\$
    – user57037
    Dec 27, 2019 at 4:34
  • \$\begingroup\$ So you connect one side of a switch to 12V, and the other side to the input pin. You press the switch and now the input pin sees 12V and reads high. You release the switch, and the input pin still sees 12V because it's a capacitor. So it still reads high. Then what? \$\endgroup\$
    – user253751
    Dec 27, 2019 at 13:18
  • \$\begingroup\$ Its not necessarily RF interference that causes this, thats a new one on me. So trying to fix mcu designs as a result is not the right path. you solve this with resistors which is in part why they are sometimes included in the gpio pad. \$\endgroup\$
    – old_timer
    Dec 27, 2019 at 14:35
  • 2
    \$\begingroup\$ "...then it causes logical reading floats. I wonder could this problem be solved..." - it's not a problem for logical reading. If the input is floating then its state is undefined, which is correct, and software should ignore the logic level - just as it should for undefined bits in internal registers. It may cause increased current draw or interference from EMI injection, but these are not logic problems. \$\endgroup\$ Dec 27, 2019 at 17:05
  • 2
    \$\begingroup\$ RF interference? Sometimes just sweeping a hand over an MCU having a floating I/O input can switch its logic state. It takes very little static charge to do this. \$\endgroup\$
    – glen_geek
    Dec 27, 2019 at 23:14

6 Answers 6


tl;dr increasing IO rail swing has drawbacks, and also doesn't help because static charge can still swing to either rail.

To start, there are tons of practical reasons why we don't just increase I/O voltage. It's not as simple as some guy crossing out 3.3v on a piece of paper and writing 12v instead. Modern CMOS processes for processors are designed to create thin gate oxides for fast, low-voltage devices. The processing steps needed to grow a thick gate oxide would be both costly and adversely affect performance and yield. The nice thing about a lot of cheap ICs is that they have a simple process--a 3v3 chip might have all gate oxides grown to withstand 3.3v+safety factor. You've now introduced multiple new masks (plus photoresist and etching steps), perhaps doubling or tripling the price of the chip.

Likewise, power dissipation for high-speed circuitry would be an issue. Especially for fast signals, high voltage swings imply high power dissipation (on the order of voltage squared) due to capacitances and series impedances. Additionally, if you must maintain your core at 3.3v to remain within a power/thermal budget, you'll need to add level shifting, which itself generates additional heat, consumes additional power, and causes users to incur additional costs.

Your thresholds are also fairly arbitrary--a sharp 6V threshold requires a voltage comparator, which leads to its own instability problems in case of certain feedback structures that could very well arise on a floating pin. For a reasonable I/O buffer, the threshold is going to be a reflection of the gate threshold voltages of the transistors in the buffer, which ties back to our manufacturing limitations. You run into the same shoot-through problems, but they're worse now since the region where both FETs are on is wider thanks to the higher rails, and the supply voltage is higher leading to yet more power dissipation. You've made the issue worse rather than better.

Now, with all of that said, simply making I/O thresholds higher isn't going to fix the issue of floating signals. Given the amazingly high resistance of the gate oxide, a floating pin can easily reach 6V--especially given that there's a >6V rail nearby!

When all of this is said and done, we've delayed chip production by a year while we develop fabrication processes and establish contracts to do mixed-voltage systems with both high-performance cores at 1v2 and 12V I/Os. We've pushed our power budget up, meaning that we must buy more expensive heatsinks and fans, as well as larger batteries and power supplies, and we also haven't reliably fixed the issue.

Or, you could buy a tape/reel of 10000 pullup/pulldown resistors for $10 on DigiKey, or for less in Shenzhen. More likely than not, your PCB manufacturing partner already has some standard pullup/pulldown resistor on hand, loaded in their pick-and-place machines, and ready to be placed. Or, your chip might already include pullups/pulldowns, since those can be fabricated fairly easily on some processes using weak MOSFETs.

  • \$\begingroup\$ Hey thank you Monica, I am quite new to EE. I don't understand what is the meaning of "Given the amazingly high resistance of the gate oxide, a floating pin can easily reach 6V". Meanwhile, I see that there are so many downsides by increasing the threshold voltage and we don't really want to put this into reality. However, seems that increasing threshold voltage can really avoid the environment factors to cause logical reading to be high right? The higher the threshold voltage, the harder for environmental factor to make input pin reach logical high? \$\endgroup\$
    – mannok
    Dec 27, 2019 at 21:24
  • 4
    \$\begingroup\$ @mannok That's not correct. A pin can be at any arbitrary voltage when floating--ground just happens to be the lowest-voltage rail by convention. A floating pin can just as easily read logic high as logic low, or it can be at some unfortunate voltage between the rails. There's nothing magic about the ground rail, per se. Nothing says the stray charge on that pin has to cause the pin voltage to sit closer to the VSS rail than the VDD rail. \$\endgroup\$
    – nanofarad
    Dec 27, 2019 at 21:33
  • 1
    \$\begingroup\$ To be fair, the OP could have asked the same question with a more reasonable strawman (e.g. "why doesn't the chip itself contain a pull up/down resistor if one is always needed, given putting in the chip is probably cheaper than putting it a a separate discrete component"). Other than "its not the standard" I'm not sure I know the answer to that. \$\endgroup\$
    – abligh
    Dec 28, 2019 at 18:35

It has been solved already. Some microcontrollers have built in pull-up and/or pull-down resistors that can be enabled via software. But these are not active when microcontroller has no firmware so for safety reasons you might still want to have external resistors to keep stable state during powerup, reset or firmware download.


Logical reading (1 or 0) of a micro-controller may float at input GPIO pin if it is neither connecting to VCC nor GND, someone said it is because of surrounding RF interference.

Yes, and static charge.

When voltage affected by RF interference makes GPIO input pin voltage falls on undefined logical range (i.e. 0.8V - 2.2V for Raspberry PI) then it causes logical reading floats.

Yes and this can cause problems internally. In the input stages of Figure 1 below the undefined logic states can result in both the upper and lower transistors turning on at the same time. (With proper logic levels only one is on at a time.) The result is a condition called "shoot-through" and a high (for the device) current will flow through the device. This is graphed on Figure 2. This will result in overheating of the gates.

enter image description here

Figures 1 and 2 from TI's Application Report Implications of Slow or Floating CMOS Inputs.

The article goes on to explain:

Both CMOS and BiCMOS families have a CMOS input structure. This structure is an inverter consisting of a p-channel to VCC and an n-channel to GND as shown in Figure 1. With low-level input, the P-channel transistor is on and the N-channel is off, causing current to flow from VCC and pulling the node to a high state. With high-level input, the n-channel transistor is on, the P-channel is off, and the current flows to GND, pulling the node low. In both cases, no current flows from VCC to GND. However, when switching from one state to another, the input crosses the threshold region, causing the N-channel and the Pchannel to turn on simultaneously, generating a current path between VCC and GND. This current surge can be damaging, depending on the length of time that the input is in the threshold region (0.8 to 2 V). The supply current (ICC) can rise to several milliamperes per input, peaking at approximately 1.5-V VI (see Figure 2). This is not a problem when switching states within the data-sheet-specified input transition time limit specified in the recommended operating conditions table for the specific devices. [Emphasis mine.]

So, they are saying, "(1) Drive inputs to defined logic levels. (2) Switch between logic levels quickly."

I wonder could this problem be solved by how a microcontroller design. i.e. Enlarge the logical voltage range, say < 6 V for low > 6 V for high. Since interference may seldom reach such high level voltage.

That would make things worse.

  • The input impedance of the CMOS gates is so high that it would not be difficult to reach 6 V.
  • Any shoot-through now becomes a much more serious problem. In Figure 2 we can see that the peak current is 4 mA on a 5 V supply. From P = V × I we can calculate the peak power dissipated in the gate equals 20 mW. If we used 12 V logic the peak power would increase to 48 mW at 4 mA - but the actual current would probably be much higher.
  • Even with good logic levels and fast transitions the heat generated inside the chip increases with frequency because there are more transitions per second.

Over the years logic power supply voltages have been decreasing to solve the power density problems as the devices have become smaller and smaller. Where 5 V logic was standard once, we now have 3.3 V and lower to reduce power consumption and to manage heat.

The TI article is worth reading. (And your English reads very well.)

  • \$\begingroup\$ Hey @Transistor, thank you so much for the well explanation. After reading your answer, I am thinking that increasing threshold voltage can indeed fix the ambiguous logcal input since RF interference and static charge can rarely reach such high voltage level, am I right? However, although this can fix ambiguous logical reading, there are drawbacks. i.e. more energy is being consumed in shoot-through range, more heat generation, etc. \$\endgroup\$
    – mannok
    Dec 27, 2019 at 6:11
  • \$\begingroup\$ It would be useful to explain why PMOS and NMOS transistors in the CMOS stage should be both turned on in the threshold region... if this creates problems ("a current path between VCC and GND"). \$\endgroup\$ Dec 27, 2019 at 6:11
  • 3
    \$\begingroup\$ @mannok Transistor answers that question directly, and says that your supposition is wrong: "The input impedance of the CMOS gates is so high that it would not be difficult to reach 6 V." Why are you even asking the question if you will not listen to any of the answers? \$\endgroup\$
    – sdenham
    Dec 27, 2019 at 21:17
  • \$\begingroup\$ @sdenham, Doesn't the input voltage depends on my voltage supply? \$\endgroup\$
    – mannok
    Dec 27, 2019 at 21:31
  • \$\begingroup\$ Yes, the logic threshold voltages will increase with supply voltage, but so what? You still have a very high input impedance. In any case, the trend is for lower voltages for the reasons outlined above. \$\endgroup\$
    – Transistor
    Dec 27, 2019 at 23:07

There is very important rule in electronics: NEVER left anything out of control. So, if there is not strictly written in datasheet that the input has an internal pull-up or pull-down, DON'T let to have undefined state on this input. If you dont need this input, connect it to ground or Vcc, NEVER leave float. Such undefined states can cause some less or more accidental problems, very hard to investigate and solve - this is not worth to spent hours on fight them only because you want to save cost of one small resistor. This is really very bad practice. This is like car driving: always look at mirror before you stop on road.

NOTE: in case of modern MCUs the problem can be solved by configuring (programatically) unused i/o pins as output, so there is no need to connect them anywhere. But, if you changed i/o pin direction to input and there is no pull-up/pull-down inside MCU, you MUST take care on this and preserve proper pulling yourself. Float state is ARCHENEMY for us ;) ;) ;) ;)

  • 4
    \$\begingroup\$ I have yet to see an MCU that defaults all it's GPIOs to outputs. Such concept is just not workable in real designs where external circuitry wants to drive input pins. \$\endgroup\$ Dec 27, 2019 at 3:44
  • \$\begingroup\$ It depends ;) But generally you are right. Thank you, I'm fixing my answer. \$\endgroup\$ Dec 27, 2019 at 4:01
  • 2
    \$\begingroup\$ Thanks for the correction. I have removed my downvote, \$\endgroup\$ Dec 27, 2019 at 14:59
  • \$\begingroup\$ Thx a lot for removing :) \$\endgroup\$ Dec 27, 2019 at 16:58

Input immunity to stray A/m B field noise or V/m E field Noise is not determined by the DC voltage threshold, but rather the noise impedance and voltage or current of the crosstalk. The crosstalk is inductive to current noise and capacitive to voltage spike noise. It is not sensitive to DC nor does DC improve immunity.

Only the thresholds of say a Schmitt Trigger range and the input impedance define noise immunity. Otherwise the signal loop impedance with the driver impedance , Zol=Vol(Max)/Iol(Max) and the margin the nearest input threshold worst case define the power required to generate a false trigger.

Thus is also one of the reasons why the driver impedance has been designed by Industry standards for CMOS MFG’s to be lower as the Vdd max range is reduced in order to retain noise immunity.

The 3 major families are

  • 3~18V CMOS which has the highest driver impedance starting at 300 ohms and rises with lower Vdd.
  • 5.5V Logic Max is 50 to 66 Ohms +/- 50%
  • 3.6V Logic Max is 25 to 33 Ohms +/-50%

Schmitt trigger Inputs are preferred for noisy high impedance sources.

< 120 Ohm terminated impedance lines are preferred for high speed noise immunity with differential inputs.


the 'pull up' or 'pull down' resistor provides an electrical path to either negative (usually ground) and positive (usually supply voltage) when the output is not activated. It holds the output pin at that potential so that it doesn't have spurious output or unwanted wild ocscillations.(It provides a light load to the output of the chip) An unstable logic chip or OP-Amp will quite often overheat and self destruct..and if the load is capable of following the oscillations at high speed, then that is also likely to self destruct. (Think of a mechanical actuator or valve trying to work at god knows what frequency!!)

It just keeps things stable. When the output is driven by the logic processor, it cleanly changes state from high to low or vice versa...(depending on the logic and whether the output is 'tied' high or low)....when it is meant to change state.

  • 4
    \$\begingroup\$ Welcome to EE.SE. Pull-ups are used on inputs, not outputs. They appear on open collector or tri-state outputs but their function is to pull the following input to a known logic level when the open collector output is off. \$\endgroup\$
    – Transistor
    Dec 28, 2019 at 3:04
  • \$\begingroup\$ @Transistor. Pull-ups were used back when TTL had to drive CMOS inputs. The pull-ups brought the output 'high' level more into the range of a CMOS 'high. But this also could be thought of as a input problem. The common bus often had pull-ups to prevent floating if no bus driver was active. \$\endgroup\$
    – user105652
    Dec 29, 2019 at 22:54
  • \$\begingroup\$ @Sparky, I'm from those days. I remember! \$\endgroup\$
    – Transistor
    Dec 29, 2019 at 23:06

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.