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I need to connect 100Mbps Ethernet PHY signals from my main board to RJ45 connector on daughter board through an on board header like shown below.

Header on the main board

Ethernet will be used only in the board bring up phase and later we will not use it much. In main board, we are approaching this method, due to size constraint.

RJ45 connector with magnetics will be given on the daughter board.

Can you suggest me some design guidelines in this kind of approach?

Is it better to provide magnetics on the main board?

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  • \$\begingroup\$ what is the length of the connection? Later we will not use it much means you still need it after deployment? will your product go to field (certifications)? \$\endgroup\$
    – User323693
    Dec 27, 2019 at 8:00
  • \$\begingroup\$ As I can understand from the connector that you have attached, it is a discrete wire connector. The speed of your ethernet also will matter while selecting a connector. It will be better to check with the manufacturer that these type of connector can be used for differential signals like ethernet and signals up to what speed these connectors will support. \$\endgroup\$
    – shafeeq
    Dec 27, 2019 at 9:26
  • \$\begingroup\$ Use the results of your Si analysis of the signals across the boards and through the connectors to determine if it will work with an appropriate margin. \$\endgroup\$
    – old_timer
    Dec 27, 2019 at 14:29
  • \$\begingroup\$ Likely you can constrain the interface to 10megabit mode and the Ethernet is probably not a bottleneck anyway. If this is one time setup (loading an openWRT image?) you might consider a through hole footprint you could use with a pogo pin fixture in production but solder a header to for firmware development units. \$\endgroup\$ Dec 27, 2019 at 16:48

2 Answers 2

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100BASE-TX MDI will run over that connector with no problems at all in practice. It's remarkably forgiving - I've seen it run over D38999 connectors which have a much greater deviation from the 100 ohm nominal differential impedance and the reflections from the impedance mismatch only start causing functional problems when you try to make it go through more than about 5 mated pairs of those connectors before reaching another PHY (with tens of meters of intermediate cabling). I would not say the same for 1000BASE-T.

You may as well take some mitigating steps though:

  • Keep the distance between connector and PHY as short as practicable (a few inches is fine)
  • Pin assignments: Do something like GND RX- RX+ GND TX- TX+ GND to keep the characteristic impedance vaguely in the ballpark of what it should be and to reduce crosstalk. You can replace any of those GNDs with a power supply rail voltage if desired, or omit if it's at the edge of the connector.
  • Put the magnetics on the motherboard, avoiding hassles with circulating CM currents. But if that can't work due to space constraints, it'll almost certainly be fine anyway.
  • Since the connector you pictured is board-to-wire rather than board-to-board, keep the cable you use with it as short as practicable and use twisted pairs for RX and TX if it must be more than a few inches long.
  • Don't expect to get the full IEEE 802.3 100 meter network segment length out of it. Connect the daughterboard to a NIC or switch with a >= Cat5 patch cable no more than 10 m long.
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It would be better to put the phy chip and magnetics on the daughterboard and run MII\RMII to the processor (or microprocessor or hub chip or phy ect).

The header pictured above is unlikely to support differential pairs well and provide 100Ω matching for the differential pairs of the TX and RX lines required by 100base-T ethernet.

RMII and MII run at 50 and 25MHz and the header should be able to support those speeds. RMII needs roughly 10 signals (if I remember right) which you should be able to use the header above. MII might need to use a slightly larger header.

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