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I have designed the following circuit to implement CMOS logic of:

\$\text{out}=\overline{(a+b).\overline{c}+e.(\overline{f}+\overline{g})}\$

I’m looking for the optimal circuit with the minimum number of transistors, is there any better implementation?

enter image description here

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  • \$\begingroup\$ You're allowed to just make c' without counting the transistors to make it? \$\endgroup\$
    – The Photon
    Dec 27, 2019 at 17:45
  • \$\begingroup\$ @ThePhoton yes it is possible. \$\endgroup\$
    – b.j
    Dec 27, 2019 at 17:47
  • \$\begingroup\$ It's not a question of possible, it's a question of the specfications of the problem. \$\endgroup\$
    – The Photon
    Dec 27, 2019 at 17:47
  • \$\begingroup\$ @ThePhoton No, I mean that if we consider we have a,b,c,e,f,g and a’,b’,c’,e’,g’,f’ then design the above function \$\endgroup\$
    – b.j
    Dec 27, 2019 at 17:49
  • \$\begingroup\$ Yes, but does your problem specify that you get all 12 of those signals as inputs, or do you only get a, b, c, d, e, f, g? \$\endgroup\$
    – The Photon
    Dec 27, 2019 at 17:51

1 Answer 1

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The minimum number of transistors = 2x the number of variables + 1x the number of inverted inputs.

You have 12 transistors with 6 variables.

is there any better implementation?

Better in what way?

Usually ideal Logic depends on what assumptions you make and more importantly specify.

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  • \$\begingroup\$ If the minimum required is what you said, how do you implement this function with 15 transistors? \$\endgroup\$
    – b.j
    Dec 29, 2019 at 14:04

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