# Minimum number of transistors to implement CMOS logic of this function

I have designed the following circuit to implement CMOS logic of:

$$\\text{out}=\overline{(a+b).\overline{c}+e.(\overline{f}+\overline{g})}\$$

I’m looking for the optimal circuit with the minimum number of transistors, is there any better implementation? • You're allowed to just make c' without counting the transistors to make it? Dec 27, 2019 at 17:45
• @ThePhoton yes it is possible.
– b.j
Dec 27, 2019 at 17:47
• It's not a question of possible, it's a question of the specfications of the problem. Dec 27, 2019 at 17:47
• @ThePhoton No, I mean that if we consider we have a,b,c,e,f,g and a’,b’,c’,e’,g’,f’ then design the above function
– b.j
Dec 27, 2019 at 17:49
• Yes, but does your problem specify that you get all 12 of those signals as inputs, or do you only get a, b, c, d, e, f, g? Dec 27, 2019 at 17:51

The minimum number of transistors = 2x the number of variables + 1x the number of inverted inputs.

You have 12 transistors with 6 variables.

is there any better implementation?

Better in what way?

Usually ideal Logic depends on what assumptions you make and more importantly specify.

• If the minimum required is what you said, how do you implement this function with 15 transistors?
– b.j
Dec 29, 2019 at 14:04