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I know that an input pin has a high impedance, but how a high impedance makes such pin be so sensitive?

According to https://forum.arduino.cc/index.php?topic=454553.0 -- #4 mentioned

If the input impedance is too high, say 100MΩ, then you'd need only 50nA to get 5V. This would make the input far too sensitive

Yes I know the calculation and this indeed follows the ohms law. However, my question is that in order to make the pin read a HIGH signal, what can the pin control is that "how much current should it draw" but not "how much voltage can the environment apply". From my understanding, as long as the environmental factor cannot provide 5V, the 100MΩ can never take 5V. (Logical reading should depends on the input voltage applied but not how much current drawn!)

Base on my assumption above, my questions are:

  1. How can a high impedance input GPIO be so sensitive if the the environmental factor(volt) cannot be controlled by the GPIO pin? (just like you won't get a 5V circuit from a single 3.7V 18650 battery)
  2. is it a truth that environmental factor can make a 5V voltage difference into the high impedance GPIO input pin? From my understanding, as long as the environmental factor cannot provide a 5V voltage difference (say 1V only), that GPIO shouldn't read a HIGH signal.
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However, my question is that in order to make the pin read a HIGH signal, what can the pin control is that "how much current should it draw" but not "how much voltage can the environment apply".

We don't "make" a pin read a signal by drawing current from the pin at that moment. The input buffer is always reading the signal, and our microcontroller chooses to act upon it in a certain way. Here's an example of what a GPIO's input buffer might look like:

enter image description here [source]

Notice the devices Q1/Q2/Q3/Q4. They are FETs, short for field-effect transistors, meaning that they conduct based on an electric field related to the gate, or the pin at the left connected to 'A', the input.

Assume 5V logic. Q1 is designed so that it conducts when its gate has a lower voltage than VDD (i.e. +5v). Q2 is designed so that it conducts when its gate has a higher voltage than VSS (i.e. ground). When the signal is driven to either logic high or logic low, either Q1 or Q2 conducts, never both. This creates a signal at the gates of Q3 that is logic low or logic high, respectively, making the same guarantee for Q3/Q4. Thus, the output 'Q' is valid.

Now let's imagine that 'A' is at around 2 V, e.g. because it's floating. Now, Q1 is conducting since 2 volts is less than 5 V, and Q2 is conducting since 2 V is more than 0 V. We've created a short circuit where power is connected to ground through Q1 and Q2, which could cause unusual currents to be drawn, instability of the whole chip, or even physical damage. Moreoever, Q3 and Q4 now have an invalid input so 'Q' is also invalid, as well as anything inside the chip that relies on the value of Q.

There's a physical reason for why these charges can persist. Recall that a FET is a field-effect transistor, whose behavior is mediated by a physical electric field. Here is the construction of an N-channel MOSFET (such as Q2 in the diagram):

enter image description here

[source]

Notice how the gate is separated from the source and the drain through a layer of oxide (the grayish rectangle). This oxide is an amazing insulator. When the transistor is "on", there's excess charge build-up on the gate, which causes changes to the energy levels in the channel allowing current to flow. The important thing is that the gate is a dead-end to electrons, meaning that they can't go anywhere. Almost no current is drawn, and even small stray charges can influence the behavior of a floating pin.

In fact, the oxide is such a good insulator that we can use floating signals for technological benefit, in special applications. Flash memory (as seen in SSDs) contains a large number of special MOSFETs with their gates floating. By using special physical phenomena to inject a charge into those gates, we can keep a charge on a floating node for years as a form of data storage.

However, a raspberry pi GPIO isn't a flash cell, but rather an exposed pin. By a number of physical phenoma, both internal to the chip and external such as RF and static buildup, charge is easily, yet unpredictably injected onto the gates of input FETs. If the signal isn't driven with either a pullup/pulldown or some sort of input signal, the voltage on the pin will be unpredictable and will lead to the issues described above.

How can a high impedance input GPIO be so sensitive if the the environmental factor(volt) cannot be controlled by the GPIO pin? (just like you won't get a 5V circuit from a single 3.7V 18650 battery)

This sentence doesn't make a lot of sense to me. A GPIO on a CMOS-technology chip is sensitive because it measures voltage, without needing to draw much current from the pin.

is it a truth that environmental factor can make a 5V voltage difference into the high impedance GPIO input pin? From my understanding, as long as the environmental factor cannot provide a 5V voltage difference (say 1V only), that GPIO shouldn't read a HIGH signal.

It is true that an environmental factor can place a 5V voltage onto a high-impedance pin. The little shocks we get when we accidentally drag our shoes on a carpet and then touch a doorknob are easily in the kilovolt range. There are ESD protection networks inside the GPIOs such as the following:

enter image description here [source]

While they bleed off any excess voltage outside the rails, they don't actually solve the problem of floating signals. I could pick up a stray 400 V charge from walking around, and then touch a floating input pin on a circuit connected to a 5 V power supply. As I transfer charge, they clamp the pin voltage to between 0 and 5V, meaning that depending on the polarity of the charge on my hand, I could force the pin high or low.

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Most modern chips have CMOS structure so they are not driven by current in or out, but voltage at a pin. CMOS input stage is basically a pair of FET gates and FET gates can be mostly seen as very small capacitance. So it takes very little charge into very small capacitance to accumulate enough voltage to make the input change between logic 0 and 1. Static electricity is enough, or a finger touching the pin. Or leakage current from nearby traces, via conducting dirt such as flux residue or moisture. Or just stray capacitance.

Since the chip is not absolutely perfect itself, there will be leakage currents inside the chip into IO pin. Maybe nanoamps or femtoamps, but there are. There can be different paths, one to pull voltage towards VCC and another to pull voltage towards GND. And they are temperature specific. So it is possible (and has happened) that a floating pin has stable reading at some logic level when cold and stable reading at another logic level when hot so it only works at certain temperature (e.g. device boots only when cold, or only boots when warmed up first)

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