I'm making a sample-and-hold circuit for a 3 bit Flash/Parallel ADC and to allow the conversion to have enough time to happen I want to maintain the input voltage steady for the duration the conversion will take. I intend on sampling an audio signal from a phone or mp3 player.

I'm simulating the circuit first and I'm having some trouble with the output from the sample-and-hold part. Sample and hold cicuit in Proteus

I'm using the LM358N opamp for the buffers and an IRL520 NMOSFET to switch. The opamps are on dual 9V, -9V supply

To switch the MOSFET, I'm using 0 and 9V signals at 1kHz and the input signal to the buffer is a 6V peak to peak sine wave at 500Hz.

Ideally, the output should be a staircase looking waveform but with my holding capacitor at 1uF the signal is distorted. This is the scope output at 1uF. Scope output at 1uF I've tried quite a few different values for the capacitor to little success.

I initially thought it was due to the switch resistance forming a low pass filter with the capacitor but it Rds is pretty low (0.18 ohms).

My question is why is this happening and how do I solve it. I know I'm a bit new to asking questions here so if there's anything useful I've left out please let me know. I'd really appreciate any help in solving this.

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    \$\begingroup\$ A 1uF cap and an IRL520uF are enormous for a sample and hold application. The gate and output capacitance of the FET and the large hold capacitance will certainly be problematic. Have you calculated how much capacitance you need to hold your signal between samples? \$\endgroup\$ – John D Dec 29 '19 at 20:01
  • \$\begingroup\$ And for what there is R10? It does nothing... \$\endgroup\$ – VillageTech Dec 29 '19 at 20:11
  • \$\begingroup\$ @JohnD I calculated the capacitance based on the hold time to be 10us, I used the time constant of the MOSFET resistance and the capacitor as the first opamp had close to 0 output impedance. So with the 0.18 ohms and the desired 10us and an accuracy of 10 percent I think that would require a capacitor of about 18.3uF. I tried that in the simulation but the output was in millivolts and triangular. \$\endgroup\$ – choco_squirell Dec 29 '19 at 20:31
  • \$\begingroup\$ @VillageTech the resistor R10 is an overall feedback resistor, its to keep the feedback current from the second buffer to the first at a minimum. \$\endgroup\$ – choco_squirell Dec 29 '19 at 20:41
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    \$\begingroup\$ R10 is connected between outputs of both OP-amps. So, it doesn't make/provide any feedback. \$\endgroup\$ – VillageTech Dec 29 '19 at 20:43

Using a transmission gate or Analog Switch enter image description here

The S&H design specs MUST be done before any serious design; e.g.

Vin range, f range, Zs source impedance, aliasing filter requirements, sampling rate SNR, N bits accuracy and sampling error i.e. a total error budget

Here I will just highlite sampling errors.

For example if Analog Op Amp has a current limit or emitter resistor of 220 Ohms, it will result in a rise time to 64% of target = RC during the sample time

  • choose the smallest C that does not decay more than dV in dt due to buffer bias current
  • choose the lowest CMOS input bias current.
  • choose non-piezo electric caps like plastic MF or NP0/C0G as all others* have a "memory" effect (ceramic*, electrolytic)
  • the sampling ratio and signal resolution in bits of Fs/Fmax greatly affects the anti-alias (Nyquist filter) steepness so be generous. (proof not shown)


Problems in your design.

  • Sampling error time 5% of 2ms (=1/500Hz = ) means in 100us the cap reaches the input voltage. so if dt=100us then choose C = Ic dt/dV . Unfortunately it is not limited by RdsON but the Op Amp current limit so this is a poor combination of Op Amp and sample cap. The output current could be increased by 100 with complementary emitter followers inside the feedback loop. The cap could be reduced to 100pF or more with metal film or C0G ceramic. The Buffer Op Amp must be changed to CMOS which also may have lower drive current so choose wisely.

Sampling at 2x the maximum frequency means you can capture the correct peak amplitude ONLY if the sampling rate is in sync with the signal. They don't stress that they Nyquest Theory basics of 2f does not include signal quality. So consider a much higher sampling rate with your quantization bits =3x or More fmax.

There exists a mathematical relationship for quantization noise relating to Nyquist Theory and SNR and N bits.
Search for it.

  • your FET is polarized and relies on Vgs >>2 Vt where Vs includes the signal, so this should be replaced with a CMOS TG. (analog switch 4066 or better low R)

enter image description here

enter image description here

If you are concerned about matching input bias offset voltage consider sample interval ,dt , quantization error =dV , Buffer Input bias current, Ic so that dV/=dt*Ic/C

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  • \$\begingroup\$ I would suggest/stress the need for a CMOS op amp in a sample in hold circuit. Yes Tony, you did mention choosing the lowest CMOS input bias current, but I think input impedance is important too. My favorite op amp for SAH circuits(where common mode input allows) is the LMC660/LMC662, with an input impedance of over a TOhm and typical input bias/offset currents in the fA range. The biggest problem for a beginner is getting the layout correct when dealing with those levels of impedance/current. \$\endgroup\$ – GB - AE7OO Dec 30 '19 at 0:47
  • \$\begingroup\$ Yes and to think @GB-AE7OO 40 yrs ago we had to find other ways to make high speed S&H. But Zin and Input bias current is almost the same thing as the LMC660 has Ultra Low Input Bias Current: 2 fA \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Dec 30 '19 at 1:04
  • \$\begingroup\$ Well I'm not quite that old, but I agree. Yes, to you or me they do have almost the same meaning, but it's obvious the OP has neither the experience or training to co-relate them. I'll be truthful, when I see one of your answers, I have to slow down and READ it, more than once. And then after reading various references, I may have a chance to understand it. I always learn something new. \$\endgroup\$ – GB - AE7OO Dec 30 '19 at 1:15
  • \$\begingroup\$ I think that the OP's circuit is overally complicated for what he wants, at the frequency involved, I would just go with a analog switch(4066 or the like), a good cap(poly film (I would avoid Mylar), finding NP0 ceramics larger than about 200pF gets expensive) and a good CMOS op amp as the buffer. It's not like we are dealing with some type of exotic signal here...:) \$\endgroup\$ – GB - AE7OO Dec 30 '19 at 1:29
  • \$\begingroup\$ @GB-AE7OO I always consider >10th harmonic of sampling rate so yes any Analog switch like 4066 family will work with CMOS Op Amp and any plastic cap with very small layout area loop currents or NPO for low tolerance accuracy if/when needed. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 10 at 17:13

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