# In Verilog, does an event control always execute once at the beginning?

As illustrated in the image below, there is an event control with the variable r (for reset). I have not initalized c in the top module, but it shows in simulations that it starts at a low state. The only reason I think this is is due to the c output being set to 0 from the always @(r) statement. Why does this execute if r does not change? Or is it technically 'changing' when I initialize it in my simulation?

Variables of the type 'reg' start simulation with the value of 'x'.

Any assignment after that, also an initial assignment, will be seen as a change and will trigger the always @(r) statement. Thus your c can change at time 0.

Having said al that: you code is behavioral and can not be synthesized as you have multiple drivers for c.

Additionally the behavioral code is open to race conditions: if clk rises and r changes at the same time it is undefined in which order the two statements will be executed.

Besides all that your c is reset if r changes. Thus not only from 0 to 1 or from 1 to 0 but also any x or z change. There is no actual logic which can implement that in reality.

There are standard code templates in Verilog how to make a register with an asynchronous reset:

always @(posedge clk or posedge reset)
if (reset)
c <= 1'b0;
else
c <= ....


Last but not least:
Do not post picture of code. Paste the actual code. A prime example is this one where I would have had one hell of a time spotting the back-quote if the the user had not, correctly, pasted the original code in the question.

Time 0 initialization is not well defined in Verilog. Since r is defined as a wire, some simulators start all wires in the z state. Then if your testbench drives it with an uninitialized variable in the x state, there is a z to x transition at time 0.

Your code is not using a named event. That requires declaring a signal with the event data type. You are using an event control. That means what for the expression after the @ to change from any value to another. You probably want to combine that with the other always block as in

always @(posedge clk or posedge r)
if (r)
c <= 1'b0;
else
c <= ...
`

BTW, it would really help to post your code as formatted text instead of a picture of the code.