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I have designed a power supply that has two outputs, one at -3kV (200mA) and one at -6kV (10mA). A new design challenge has arisen that includes the need to pulse both of the outputs from nominal load to 0A anywhere from 100Hz-100kHz with varying duty cycle. At the moment, although the primary side switches have a frequency of 300kHz, the response to the output loading is not fast enough.

I have posted in other forums and some have mentioned that high-speed linear regulators are able to negate the effects of the load transient. However no-one has been able to assist with a possible circuit for me to attempt to implement. I will attach a schematic which shows what I have so far, without any secondary side control.

I have spoken to some engineers who say that pulsing the input of a linear regulator causes the pulse to be reproduced on the output, however I haven't got much experience with linear regulators to understand what this means. I attempted to do something like this in LTSpice, which I have also attached, but the voltage stresses on the components are too severe and I don't know if this is at all on the right track. I will attach that schematic and results also.

Has anyone dealt with pulsed loads with linear regulators before? Has anyone got any advice to effectively regulate the voltage across the load when the output is pulsed in such a way?

schematic

result_pulsedlin

pulsed_lin

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  • \$\begingroup\$ I don’t see any question. \$\endgroup\$ – winny Dec 31 '19 at 11:38
  • \$\begingroup\$ Okay, updated. I thought it was obvious what I was asking but I have clarified. \$\endgroup\$ – jvnlendm Dec 31 '19 at 12:38
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    \$\begingroup\$ Have you considered to have bulky capacitors on the output to prevent the voltage from falling during loads. The linear regulator idea wont work if your input voltage is not stable enough. \$\endgroup\$ – Navaro Dec 31 '19 at 14:43
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    \$\begingroup\$ Still not clear. You are dropping less than 1% under stepped load. Is this a problem? If Ed, state your requirements. \$\endgroup\$ – winny Dec 31 '19 at 14:52
  • \$\begingroup\$ What is this supply powering? Your 3kV output appears to be referenced to the rectifier output, not to ground. Does this mean its load is floating? How smooth and accurate do the output voltages have to be, and how fast must the PWM rise and fall times be? In your simulation you have a 220nF capacitor across the load. Why? \$\endgroup\$ – Bruce Abbott Dec 31 '19 at 21:59
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Source Impedance as a function of frequency can be measured that is inverse to load regulation. The open loop impedance can be defined by RdsOn or Rb/hFE. Closed loop impedance reduces output impedance less with rising frequency due to a fixed GBW. This is reduced further by a shunt array of low ESR capacitors as long as it results in a stable "servo" voltage. Some CMOS LDO's have boundary conditions for stability with ESR.

Load regulation error tends to be nonlinear due to internal effects, and to remain practical often a pre-load helps with overshoot or minimum load is expected. This testing and PS specs is done with useful step loads such as 20~100%, 100~50%.

For pulse loads that exceed static power ratings, bulk storage reactance (caps) are necessary.

Where pulse width and frequency have unstable zones of nonlinear error, one has to examine the power Supply Bode plot for gain phase margin with sinusoidal swept frequency current loads. This is called Spectroscopy. This can be useful to analyze materials or find design faults in the regulator components that affect error and feedback.

Has anyone got any advice to effectively regulate the voltage across the load when the output is pulsed in such a way?

That needs to be defined by empirical specs and test results where it fails.

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  • \$\begingroup\$ I'm sorry, I am in my first year of a PhD and some things you mention do not make much sense to me. Why does source impedance come into the picture when considering pulsed loads? What is a pre-load? I do not understand the spectroscopy comment. Do you have any suggestions, circuit wise, that could help me out with the pulsed load on the secondary side when consdering HV? \$\endgroup\$ – jvnlendm Jan 1 at 17:41
  • \$\begingroup\$ Consider all Linear Op Amps have fixed GBW and PSRR depends on frequency. When the regulator cannot respond fast enough to eliminate error for input , then bulk caps must bypass this dV/dt=I/C with low ESR. to improve PSRR vs f or rise time. Same for output impedance. All transistors have a minimum (due to size) called Rce when saturated just like RdsOn on FETs or change in Vol/Iol due to load change or in linear range as emitter followers have Zo /feedback gain that determines load regulation error. Spectroscopy is an offshoot of Bode Plots which are used to determine regulator stablity \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 1 at 20:15
  • \$\begingroup\$ I'm sorry too, some important details in your comments should be in an itemized list of design specs in question. Why is Tr1 primary not bipolar with V+ to centre tap then dual Nch switches to balance primary bipolar flux. Does it saturate primary with average DC current? Maybe you need a better model and/or interactive simulator tinyurl.com/wxyonjb \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 1 at 20:54
  • \$\begingroup\$ Need bigger caps ? avx.com/products/film-capacitors/power-film-caps/… \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 1 at 20:59
  • \$\begingroup\$ Yes very true, I will update my question tomorrow with additional things in comments that may be better to describe the problem.L-O-L those are big capacitors, I have not seen any like those before. Maybe I will put a few of those in and all my issues are solved. :) Very interesting circuit you have given - how does it work, exactly? It looks very similar to the one I posted. Same issue as well, as it most likely is not good for HV output. No? I am unsure about your comments RE the Transformer configuration. I do not believe half bridge needs centre tap Primary for flux cancellation? \$\endgroup\$ – jvnlendm Jan 1 at 22:38

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