# How does an SR Latch get started [duplicate]

Noob question, but I'm not seeing how an SR latch such as the one in the image can "get started". If each input depends on the output from the other, how can there be two inputs to each gate to set the thing in motion?

In a rudimentary circuit consisting of exactly one NOR-based SR latch, what happens when the power is switched on (e.g. battery connected)?

• In many digital logic circuits, there will be an external reset line available, either active-low or active-high. This reset line is usually active during the first part of the power-on sequence, and allows whatever circuit you have to enter a defined state. In your case, you could OR-gate the reset line in with either the S or R of your latch if a known state is desired on powerup. - One such way to create a reset line is to put a RC circuit across vcc and gnd, then make reset active when voltage across the capacitor is less than a threshold. – Tyzoid Jan 2 at 17:33
• Does this answer your question? What is the beginning state for Q in a SR latch? – bwDraco Jan 2 at 20:17

## 6 Answers

It is true that the latch will "wake up" in an unknown state. In the real world, given a little time, the latch will have a valid state with either Q=0 or Q=1.

You make the latch "get started" by setting one of the inputs (R or S) to be a 1 while the other input is a 0. This will force the latch into a known state, regardless of whatever the previous state of the latch might be.

In other words, if you want to know the state of the latch then you must explicitly Set or Reset the latch.

• Depending upon the technology, an SR latch may "power up" and remain in an invalid state indefinitely until R or S goes high. This may be particularly likely with some forms of low-voltage logic. If a latch is switching at the moment VDD goes away, both outputs may be at about 0.6 volts. If VDD is 1.2 volts, the outputs may not be low enough to turn on the high-side drivers, nor low enough to turn off the low-side drivers. Such situations may not be terribly likely to occur, but many battery-powered devices include a "reset" button to force a recovery from them. – supercat Jan 1 at 22:39
• The unknown state is denoted with x in logic synthesis. Similarly, z denotes high-impedance (i.e. input disconnected). – MooseBoys Jan 1 at 23:34
• @supercat even in the low-voltage case, you'll still have four transistors operating in the linear region which creates a smaller, but non-zero current flow to the outputs. It may take 100x the normal switching time but the setup is still an unstable equilibrium that will eventually stabilize to one state or the other. Unless you have some absurdly high fanout capacitance. – MooseBoys Jan 1 at 23:47
• @MooseBoys In every synthesis tool that I have used, X indicates a "don't care" condition. There's no point in trying to synthesize an unknown state. – Elliot Alderson Jan 2 at 0:57
• @supercat "On" and "Off" are just simplifications of the true characteristics of a transistor. A PN junction will still pass current below 0.7V, albeit at an exponentially smaller magnitude as you drop further below Vt. It's still enough to charge/discharge the relatively small gate capacitances involved though. – MooseBoys Jan 2 at 2:32

When you power on a bi-stable element like a NOR SR latch (with inputs at 0) it will start at to some state. That is not necessaraiy a 'binary' state, the the outputs can for instance be halfway between 0 and 1.

Most bi-stable elements are designed with a positive feedback factor, which means that any difference between the two outoputs (or, same thing but different viewpoint: any difference between an output value and the 'halfway' point) is amplified, so the element quickly 'drifts' towards one of the two stable binary states.

This 'drifting' time can be observable, and can in some circumstances involve osscilation.

This is a way of power-on-resetting a RS latch to a known state. Problem with it, the speed of the latch is slowed down and so can only be used for low frequency applications.

simulate this circuit – Schematic created using CircuitLab

(lets assume that the two inputs of the circuit are tied to ground)

what happens when the power is switched on (e.g. battery connected)?

At an electrical level a logic gate is effectively a crude amplifier. In the SR latch circuit the amplifiers are connected together in positive feedback. This creates a circuit with an unstable equilibrium. If the output voltage is above the equilibrium point then it will rise until it saturates at a logic high. If it is below the equilibrium point then it will fall until it saturates at a logic low.

If there was no noise and the design was perfectly symmetric then by symmetry the output would sit at the equilibrium point. In the real world there is always assymetry and noise, which will push the output away from equilibrium and then positive feedback will take over and push the circuit to a saturated state. Which of the two states it ends up saturated in is unpredictable and may also be inconsistent.

How long this will take depends heavily on the particular logic family, with most oldschool logic it will be very quick, however some low voltage families may have an effective dead-band in the amplification resulting in much longer settling times.

When the circuit is powered on, its state is not defined. Because of natural variations in physical hardware, the latch will eventually settle into either valid binary state; however, in a simulator, which assumes ideal (perfect) hardware, the latch will be bouncing back and forth or otherwise be in an invalid intermediate state (e.g. Q and Q' are both on or both off; Q' is omitted in your schematic). Even with a real circuit, some oscillation may be visible on an oscilloscope when power is initially applied to the latch, and it may take an unknown amount of time for the circuit to settle into a stable state. This is called metastability. As a result, you cannot rely on the latch being in any particular state until you explicitly set or reset it.

Transistors of the latch are not ideal. On start of the latch one shoulder will 'prevail' and the latch will switch into one of the two states.

As such situation has no predictable outcome on start, it is better to forcefully put the latch into known state.