The question is
Consider an NMOS device where all terminals are at constant voltage except the Bulk terminal. A voltage is applied to the bulk terminal (w.r.t. GND) that varies from from 0V to -Inf. What is the effect on the threshold voltage of the NMOS device?
My understanding is that
- The bulk terminal connects directly to the p-type substrate of the NMOS device.
- By driving the bulk voltage lower and lower, you attract more free holes to the bulk terminal.
- This makes it easier for electrons to accumulate near the gate and form a conduction channel.
- Thus, since it's easier for a channel to form, threshold voltage should decrease.
Is that correct?