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The question is

Consider an NMOS device where all terminals are at constant voltage except the Bulk terminal. A voltage is applied to the bulk terminal (w.r.t. GND) that varies from from 0V to -Inf. What is the effect on the threshold voltage of the NMOS device?

My understanding is that

  • The bulk terminal connects directly to the p-type substrate of the NMOS device.
  • By driving the bulk voltage lower and lower, you attract more free holes to the bulk terminal.
  • This makes it easier for electrons to accumulate near the gate and form a conduction channel.
  • Thus, since it's easier for a channel to form, threshold voltage should decrease.

Is that correct?

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This isn't correct. As \$V_{SB}\$ increases, the depletion region between the N+ implants and P body increases in width; this increases the threshold voltage as a stronger electric field is necessary to shrink the depletion region so that a channel can form.

Here's a Cadence simulation I performed against my PDK (TSMC 180nm 1.8V mixed-signal). Note that the green line (representing lowest Vth) corresponds to Vbs=0, while the red line (highest Vth) corresponds to maximum body effect.

enter image description here

Here's the schematic for my test. I performed a DC analysis sweeping Vgs to get each curve, and iterated this for seven evenly spaced (negative) Vbs values.

enter image description here

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  • \$\begingroup\$ Ah. I understand. So this is basically exactly like a PN junction. By increasing V_SB, we are basically making the body diode more and more reverse-biased and hence enlarging the PN junction. \$\endgroup\$ Jan 2 '20 at 22:28
  • \$\begingroup\$ @AlfroJang80 I believe that's correct--my educational background is more in analog design than device physics so there might be more to it that I'm not aware of. \$\endgroup\$
    – nanofarad
    Jan 2 '20 at 22:29
  • \$\begingroup\$ Thank you very much. The Virtuoso simulations were very helpful as well. \$\endgroup\$ Jan 2 '20 at 22:30

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