What is the diference between concurrent 2 “when-then”, sequential 2 “if-then” and “if-elsif” statements in VHDL?

Question

I want to create an 8 bit counter with reset button on a FPGA board. I have two signals: btn_up which is debounced and btn_center which isn't. R is an output signal which represents 8 bit counter. I want to use btn_up rising edge to increment the counter and btn_center to reset it to "00000000".
I thought there are 3 ways to do it, but only one of them works. Here is the code:

Using concurrent statement "when-else" :

R <= R + 1      when (rising_edge(clk))          else
     "00000000" when (rising_edge(btn_center))   else
     R;

if I press btn_center R incements by 1 and doesn't get set to "00000000"

Using sequential "if-elsif" statement:

process(clk, btn_center)
begin
    if rising_edge(clk) then
        R <= R + 1;
    elsif btn_center = '1' then
        R <= "00000000";
    end if;
end process;

during synthesis I get error code 9 again

Using 2 sequential "if-if" statements:

process(clk, btn_center)
begin
    if rising_edge(clk) then
        R <= R + 1;
    end if;
    if btn_center = '1' then
        R <= "00000000";
    end if;
end process;

It works.

Why aren't these 3 ways of doing this the same in this case?

Answer 1

Why aren't these 3 ways of doing this the same in this case?

The behaviour of the three codes is NOT identical.

Number one:

R <= R + 1      when (rising_edge(clk))          else
 "00000000" when (rising_edge(btn_center))   else
 R;

R has to change on a rising clock edge, but if there is no rising clock edge it has to reset on a rising btn_center edge.
There exists no hardware with this behavior. You have register with asynchronous reset and/or set but the asynchronous input is level sensitive, not (rising) edge sensitive. Also the rising_edge of the clk has to override the reset.

Number two:

process(clk, btn_center)
begin
    if rising_edge(clk) then
        R <= R + 1;
    elsif btn_center = '1' then
        R <= "00000000";
    end if;
end process;

R has to change on a rising clock edge, but if there is no rising clock edge it has to reset on a btn_center being one.
There exists no hardware with this behavior. It is some sort of register with asynchronous reset and/or set but the asynchronous behaviour is overridden by a clock edge.

Number three:

process(clk, btn_center)
begin
    if rising_edge(clk) then
        R <= R + 1;
    end if;
    if btn_center = '1' then
        R <= "00000000";
    end if;
end process;

This one we have to deal with differently. You have two independent 'if' statements so the second one overrides the first one. Hence we have to start with the second one:
If btn_center is one R is set to zero, else if there is a rising edge R is incremented.
This is a typical register with an asynchronous reset

Answer 2

One additional point that the accepted (correct) answer doesn't cover:

Notice the differences come from the implementation details, not the different styles of statement.

For example you could implement solution(3) in the style of (1) as:

R <= "00000000" when btn_center = '1' else
      R + 1  when rising_edge(clk);

This gives the asynchronous reset priority over the clocked increment, just as the later assignment in process (3) does. You'll get the same behavior in simulation, and MOST modern synthesis tools should accept it and generate the correct hardware.

A similar transformation (reset branch first) is possible in process (2) which is the "standard" solution accepted by all tools.

So - get the implementation right, and there is NO difference between the statement types in this example.