I want to create an 8 bit counter with reset button on a FPGA board.
I have two signals: btn_up which is debounced and btn_center which isn't. R is an output signal which represents 8 bit counter. I want to use btn_up rising edge to increment the counter and btn_center to reset it to "00000000".
I thought there are 3 ways to do it, but only one of them works. Here is the code:
Using concurrent statement "when-else" :
R <= R + 1 when (rising_edge(clk)) else "00000000" when (rising_edge(btn_center)) else R;
if I press btn_center R incements by 1 and doesn't get set to "00000000"
Using sequential "if-elsif" statement:
process(clk, btn_center) begin if rising_edge(clk) then R <= R + 1; elsif btn_center = '1' then R <= "00000000"; end if; end process;
during synthesis I get error code 9 again
Using 2 sequential "if-if" statements:
process(clk, btn_center) begin if rising_edge(clk) then R <= R + 1; end if; if btn_center = '1' then R <= "00000000"; end if; end process;
Why aren't these 3 ways of doing this the same in this case?