I'm new to VHDL and I'm trying to use code off a teacher's slide that doesn't seem to work as is, and I can't tell what's wrong:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Add4 is port ( Data1, Data2 : in std_logic_vector(3 downto 0); Cin : in std_logic; Cout : out std_logic; Sum : out std_logic_vector(3 downto 0) ); end entity Add4; architecture RTL of Add4 is signal Out5bit : unsigned(4 downto 0); begin Out5bit <= ('0' & Data1) + ('0' & Data2) + Cin; Sum <= Out5bit(3 downto 0); Cout <= Out5bit(4); end architecture RTL;
The error I'm getting is:
add4.vhd:15:28: no function declarations for operator "+" add4.vhd:16:17: can't match slice with type array type "std_logic_vector"
The first error goes away if I comment out the assignment of
Out5bit and the second goes away if I comment out the assignment of
Sum. What am I doing wrong? Would this code have worked without being modified on some older version of VHDL or did my instructor just give me bogus code?