I am trying to design a common source amplifier and getting stuck during the design process. Was wondering if anyone can help me out. Ill show my process with comments and if anyone can show me the underlying flaw that would be highly appreciative.

Using this topology With:

\$ V_{in}=1V_{pp} \$

\$ Assuming,\lambda = 0 \$


simulate this circuit – Schematic created using CircuitLab

The process -

Design Spec:

\$ P_{Output} = 5W \$|

\$ R_L = 8\Omega \$

  1. Start by to see how much voltage I need at the output to deliver 5W into the 8Ohm load.

    \$ P = \frac{V^2}{R}\$

    \$ 5W = \frac{V^2}{8\Omega}\$

    \$ V = 6.325V\$, thus at the output I would need a 6.325V to see 5W into a 8ohm load. VDS = 6.325V

  2. Now I would use Large Signal analysis to see whats the current I need in the drain to achieve such a voltage drop across RD in order for VDS = 6.325V using KVL.

    \$ V_{DD} = V_{DS} + I_D*R_D \$

    \$ \frac{V_{DD}-V_{DS}}{R_D} = I_D\$, but in order to get RD I need to see the transfer function of this circuit. Come back to this equation.


simulate this circuit

  1. using small signal analysis to obtain the gain of the circuit

    Obtaining Branch 3:

    \$ \frac{V_o}{V_D} = \frac{Sc2}{\frac{1}{RL}+Sc2} \$

    Obtaining Branch 2:

    \$ V_D[Sc2+\frac{1}{RD}]+gmVgs = Sc2Vo \$

    Obtaining Branch 1:

    \$ \frac{V_{gs}}{V_{In}} = \frac{Sc1}{\frac{1}{R1}+\frac{1}{R2}+Sc1}\$

    Obtaining Overall Transfer Function:

    \$ \frac{V_o}{V_in} = \frac{-S*C2*RD*RL*gm}{S*C2*RD+S*C2*RL+1} * \frac{Sc1}{\frac{1}{R1}+\frac{1}{R2}+Sc1} \$

    Here's where I am stuck. Where does one find Gm? Without knowing what VGS is yet how do you find what R1 and R2 is?

    However if I where to have all the values I would essentially plug in everything and find RD. Once rd is found ill go back into that KVL question above, find the needed Current then use the \$ I_{Dsat} \$ equation to find the acquire vgs to allow current to follow into the drain that will allow my desire voltage drop across RD.

    Please let me know what Iam doing wrong. This been driving me crazy for the past week. I read almost everything online and read some textbook still not understanding. This is where I am at.


simulate this circuit

  • \$\begingroup\$ If you mean 5W "RMS", that 6.35V is an RMS voltage. Peak will be sqrt(2) * that = 9V, and peak to peak will be 18V. That's a lot to expect from an 11V battery. There are other problems too, but... \$\endgroup\$
    – user16324
    Commented Jan 5, 2020 at 22:00
  • \$\begingroup\$ Correct, thats what I mean. I can always increase VDD. Ill do it now. \$\endgroup\$
    – Leoc
    Commented Jan 5, 2020 at 22:06
  • \$\begingroup\$ @BrianDrummond what does 5W "RMS" mean? \$\endgroup\$
    – Andy aka
    Commented Jan 6, 2020 at 8:38
  • \$\begingroup\$ @Andyaka yes I should explain. "RMS" power measurements are common, but they are a misnomer, they are really average (not RMS) power, calculated from an RMS voltage measurement. \$\endgroup\$
    – user16324
    Commented Jan 6, 2020 at 12:58

1 Answer 1


You want 5W across \$8\Omega\$ speaker. So we need \$I_L = \sqrt \frac{P}{R} = 0.790\$mA of RMS current or 1.2A peak current. This correlates with a voltage drop across the speaker 9V peak. So we need \$V_{DD}\$ larger then 18V but you choose 25V.

Next, we need to select the \$R_D\$ resistor value. For this type of a circuit, the maximum positive current at load is equal to:

\$IL_{max} = I_{D} \times \frac{R_D}{R_D + R_L}\$ (1)

And additional we want

\$I_{D} = \frac{0.5 V_{DD}}{R_D} \$ (2)

And now we can solve for \$I_D\$ current (quiescent current) and \$R_D\$.

$$I_D = \frac{V_{DD} \times IL_{max}}{V_{DD} - 2IL_{max}\times R_L} \approx 5.2\text{A}$$ $$R_D = \frac{0.5 \left(V_{DD} - 2IL_{max} R_L\right)}{IL_{max}} - R_L \approx 2.2\Omega$$

But I do not like the results and decide to pick \$ R_D = 4.7\Omega\$ and \$I_D = 1.2\text{A} \frac{8\Omega + 4.7\Omega}{4.7\Omega} = 3.25\$A

The power dissipation in \$R_D\$ resistor is \$50W\$ so we need a very big resistor.

And the power dissipation in MOSFET will also be equal to 33W. So you need a big heatsink as well. Because the efficiency of this amplifier topology is very low (6.25%).

Of course, we need a capacitor in series with the speaker.

\$C_{OUT} \approx \frac{0.16}{F*R} \approx \frac{0.16}{20\text{Hz}*(8Ω + 4.7Ω)} \approx 680μ\text{F}\$

Now we need to choose a voltage divider resistors at the gate.

This type of biasing network (without \$R_S\$ resistor) is very poor and should never be used in real life. Why?

Because of the MOSFET \$V_{GS}\$ variation. Every transistor will have a slightly different \$V_{GS}\$ value at the same drain current. Also, we have a big power dissipation in a MOSFET hence the \$V_{GS}\$ will change with the temperature (Vgs will drop with the temperature and increases the drain current). So there's a chance of a thermal runaway.

As for your small-signal analyze is a way to complicated. The stage gain will be equal to

\$A_V = gm \times R_D||R_L\$

The input impedance will be \$ R_{IN} = R_1||R_2\$

And the capacitors are just AC coupling capacitors (high pass). The value of a coupling capacitor is calculated with the lowest frequency you want to amplify (half-power gain -3dB). And for the input cap \$C = \frac{1}{2 \pi F * R} = \frac{1}{2 \pi 20\text{Hz} * R_{IN}}\$

But ok, you should never build this amplifier in the real world.

MOSFET Biasing Problems

The better topology for Class A amplifier is this one


simulate this circuit – Schematic created using CircuitLab

  • \$\begingroup\$ Good summary of the other main problems. \$\endgroup\$
    – user16324
    Commented Jan 6, 2020 at 13:02
  • \$\begingroup\$ A better bias network would use the DC value of the drain voltage (via a low pass filter) to get some stabilisation against runaway. As the FET turns on, this reduces, reducing the gate voltage. Whether that's good enough ... simulate. \$\endgroup\$
    – user16324
    Commented Jan 6, 2020 at 13:12
  • \$\begingroup\$ Thank you for this, just have a few question. I thought in Saturation VDS has no affect on the Drain Current. Wouldnt it not be enough to find current through RD but now use the ID(sat) equation to find the VGS that will put your ID current at that level with that RD? The other people I found is that, where do you find Gm? \$\endgroup\$
    – Leoc
    Commented Jan 7, 2020 at 0:23
  • \$\begingroup\$ I guess this way will give you an arbitrary gain that you may not desire. If you where to have a gain spec then would you use the gain equation to find what RD you would need? \$\endgroup\$
    – Leoc
    Commented Jan 7, 2020 at 0:25
  • \$\begingroup\$ In this simple topology do not have freedom of chose Rd resistor if we want to meet the output power requirements. We cannot meet the gain and the power requirements at once. We would have to add another resistor to add ourselves freedom of choosing the gain. Because now we have to trade-off between gain and the output power. \$\endgroup\$
    – G36
    Commented Jan 7, 2020 at 16:29

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