# How does interdependent state logic work?

I'm deriving the logic for an up-down counter and have equations which connect bit states $$\Q_{n+1}\$$ to previous states $$\Q_n\$$. On each rising clock edge, the data bits of the counter change depending on the state of some UP/NOT_DOWN line and, as with all counters, the states of other bits of the counter.

I'm a little confused on how to express this logically though (for programming a CPLD), because surely, unless every bit changes instantaneously (not possible), the logic will fall apart (as the logic for one new bit would suggest "reading" the logic of an already changed bit).

Is this all part of the "timing optimization" procedure you see implementation and synthesis tools do, or is this something which needs to be considered at the design level?

EDIT: I suppose another way of asking the question would be to address whether each bit needs to be stored in some temporary storage between states, in which case, why don't we see such architectures discussed often?