I'm deriving the logic for an up-down counter and have equations which connect bit states \$Q_{n+1}\$ to previous states \$Q_n\$. On each rising clock edge, the data bits of the counter change depending on the state of some UP/NOT_DOWN line and, as with all counters, the states of other bits of the counter.

I'm a little confused on how to express this logically though (for programming a CPLD), because surely, unless every bit changes instantaneously (not possible), the logic will fall apart (as the logic for one new bit would suggest "reading" the logic of an already changed bit).

Is this all part of the "timing optimization" procedure you see implementation and synthesis tools do, or is this something which needs to be considered at the design level?

EDIT: I suppose another way of asking the question would be to address whether each bit needs to be stored in some temporary storage between states, in which case, why don't we see such architectures discussed often?


1 Answer 1


It works if the propagation delay (clock-to-Q) of the flip-flops involved is longer than the hold time of the flip-flops (plus any difference in arrival time in the clock signal between one flip-flop and another).

If this is true then when each clock cycle arrives, their outputs don't change for some time (the clock-to-Q delay). By the time the output of one flip-flop changes, the next flip-flop (whose input is connected to the output of the first one) has already "decided" what it is going to change to.

In programmable logic (CPLDs or FPGAs), this is often achieved using "negative hold time". That basically means that the next state of a flip-flop after a clock edge arrives is actually determined by the input a few 100 ps before the clock edge, rather than the input at the exact moment of the clock arrival. (Practically this really means the data is delayed by a few 100 ps from the notional input of the flip-flop to where it actually affects the flip-flop circuit)

  • \$\begingroup\$ Ah okay, thank you. Is this kind of contention guaranteed to be resolved in programmable logic synthesis, are you aware? Thanks \$\endgroup\$ Commented Jan 5, 2020 at 23:20
  • \$\begingroup\$ @BenjaminCrawfordCtrl-Alt-Tut, to be sure, you'd have to consult the documentation for your programmable device. However AFAIK for any programmable logic introduced in at least the last 25 years, it will be guaranteed. \$\endgroup\$
    – The Photon
    Commented Jan 5, 2020 at 23:22
  • \$\begingroup\$ Yes Benjamin. It is often specified as setup and hold time to clock the current input state into the next state. So synchronous counters are guaranteed. \$\endgroup\$ Commented Jan 6, 2020 at 10:30

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