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I'm getting very confused about drain source voltages and drain current in a simple common-source amplifier.

Consider the following common-source amplifier:

enter image description here

My understanding is that:

  • The output voltage is Vout = Vdd - Rd*Id.
  • If the input voltage increases by a small-signal step, then M1 will have a higher gate-source voltage, thus will increase the drain current and according the Vout equation above, the output voltage will decrease. The output voltage is the drain of M1, and so we can also say that the drain of M1 decreases.

All good so far. Here comes my confusion. If I think back to the Id/Vds plot as shown below: enter image description here

Notice that in the saturation region, as drain-source voltage increasees, the drain current increases slightly too, due to channel-length modulation. In our common-source amplifier, the drain current increased, yet the drain-source voltage (output voltage) decreased. According to this plot, how is that possible?

I would appreciate it if someone could provide a simple explanation. Where is the flaw in my understanding?

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The MOSFET doesn't stay on the same Vgs line, or the same Vds. Those Vgs lines are just a few of the infinite number on that graph for the infinite number of Vgs possible.

The MOSFET is allowed to move anywhere within that graph's space to find equilibrium. It's not trapped to one of those Vgs lines, though it may be restricted by other circuit components to traverse amongst those lines in a limited manner (like the load line drawn by the resistor).

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  • \$\begingroup\$ Can I ask one more question. If I replaced the resistor with a current-source, how would Large-Signal Vout be defined then? \$\endgroup\$ – AlfroJang80 Jan 6 at 3:03
  • \$\begingroup\$ @AlfroJang80 It would be like using a very very large Rd and a very high Vdd. DS resistance and variations of it due to changes in Vgs would be very small relative to Rd making your DS current nearly constant where I ~= Vd/Rd. Load line would be horizontal = lots and lots of gain. You need to do more involved math that substitutes in transistor model equivalent circuits to get the equation in that case. You posted equation is too simple since it doesn't even consider Vgs yet. \$\endgroup\$ – DKNguyen Jan 6 at 3:22
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The thing missing from that graph is a load line.

Let's say VDD is 6 V and RD is 15 kΩ. If the FET was a dead short (VGS = 0 V) then RD would draw 6 V / 15 kΩ = 400 μA. If the FET is cut off then it draws no current though RD and VDS = 6 V. At all points between the resistor drops a voltage proportional to the current going through it.

So we draw a straight line from 0 V and 400 μA to 6 V and 0 μA. Wherever that line intersects a VDS curve is the current and voltage across the FET at that VGS value. For intermediate points you must extrapolate to get the approximate VGS value.

enter image description here

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  • \$\begingroup\$ Bruce beat me to it as I was going to say the same last nite as a better answer. . The gain can be related to the separation between ΔVds / ΔVgs at any Id. However the load line SHUD BE in the Linear region with low Vds and NOT to the right of it. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 6 at 11:03

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