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When the device is connected to the ST_LINK, after firmware upload, it works perfectly fine. When I remove the ST_Link and then turn OFF and ON my device, it does not work, unless I initiate a hard reset.

Also, the device works fine when I chose the internal oscillators as a clock source (both with ST-Link connected and without it).

The problem only persists, when in the clock configuration, I choose the clock source and the HSE (external 8MHZ crystal oscillator). The Boot0 pin is pulled low using a 10K resistor. What is going on? The reset circuit in my device

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  • \$\begingroup\$ Try disconnecting everything but 0.1uF cap from NRST pin. Also, do you have semihosting enabled by any chance? that sometimes creates all kinds of strange behavior. \$\endgroup\$ – Maple Jan 6 at 8:04
  • \$\begingroup\$ Do you have all Vdd and VddA pins connected to Vdd ? \$\endgroup\$ – Russell McMahon Jan 6 at 9:34
  • \$\begingroup\$ @RussellMcMahon Yes. All the VDDA and VDD pins share the same 3.3V rail. I tested the crystal with an oscilloscope and it seems fine. The reset IC above seems to be doing fine since it keeps the NRST pin low for around 300ms and releases it once the VDD, VDDA reaches the required threshold as mentioned in the datasheet. \$\endgroup\$ – adnan Jan 7 at 0:33
  • \$\begingroup\$ It must work then :-) (usually :-) :-( ) \$\endgroup\$ – Russell McMahon Jan 7 at 0:49
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The STM32F072C8T7 has inbuilt POR (power on reset) capability. The datasheet notes (page 14):

  • The device has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold,VPOR/PDR, without the need for an external reset circuit.

But, is this unconditionally the case?
No, unfortunately.

  • The POR monitors only the VDD supply voltage.
    During the startup phase it is required that VDDA should arrive first and be greater than or equal to VDD. The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that VDDA is higher than or equal to VDD.

Page 14 also notes::

VDD = VDDIO1 = 2.0 to 3.6 V: external power supply for I/Os (VDDIO1) and the internal regulator. It is provided externally through VDD pins.

VDDA = from VDD to 3.6 V: external analog power supply for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC are used). It is provided externally through VDDA pin. The VDDA voltage level must be always greater or equal to the VDD voltage level and must be established first.

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  • \$\begingroup\$ I have used the same 3.3V rail for both VDD and VDDA. I think that could be the problem? Thank you for the insight \$\endgroup\$ – adnan Jan 6 at 6:44
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    \$\begingroup\$ From RM0091 reference manual for STM32F0 series: "When a single supply is used, VDDA can be externally connected to VDD, through the external filtering circuit in order to ensure a noise free VDDA reference voltage." In fact, I have never seen an STM that did not allow VDD to VDDA connection (assuming shared ground, of course). The problem is somewhere else. \$\endgroup\$ – Maple Jan 6 at 7:40
  • \$\begingroup\$ @RussellMcMahon Nothing magic about it and of course I did not cite from memory. Any ST manual can be found by simply typing MCU model and selecting pretty much first link that points to ST site. In this case it was a third link from top: RM0091. Paragraph 5.1.1, page 80. \$\endgroup\$ – Maple Jan 6 at 9:18
  • \$\begingroup\$ Just to clarify - ST datasheets only list electrical characteristics and pinouts of specific chips. The rest of documentation is in reference manuals common for entire series. \$\endgroup\$ – Maple Jan 6 at 9:24
  • \$\begingroup\$ I've deleted a comment and part of my answer. I realise I was being excessively didactic in the face of uncertainty. (And perhaps slightly rude in approach :-(). \$\endgroup\$ – Russell McMahon Jan 6 at 9:38

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