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I'm being having a lot of trouble fully grasping the interaction between NMOS and PMOS current sources. Is my understanding below correct?

Consider the following circuit in two phases,

enter image description here

Assume that M3 and M2 are at a 1:1 ratio. The bias voltage for M1 Vb is chosen to allow for 100uA.

Phase 1

  • Iref = 100uA.
  • Due to the 1:1 ratio between M3 and M2, 100uA flows through M2 and M1.

Phase 2

  • Iref increases to 200uA.
  • Due to the 1:1 ratio between M3 and M2, 200uA flows through M2 and M1
  • M1 has a bias voltage on it's gate to support only 100uA, so the drain-source voltage of M1 (=Vout) must increase to support this new 200uA current.
  • This drives M1 further into saturation and M2 towards the linear/triode region

Phase 2 Alternative Understanding

  • Iref increases to 200uA.
  • Due to the 1:1 ratio between M3 and M2, 200uA flows through M2 and M1
  • As M1 has a fixed gate-source voltage, it can be seen as a fixed ressitance with resistance of ro1. A higher current in the right-branch means, more current through ro1 and thus by Ohm's Law, a higher voltage drop and hence an increased Vout.
  • This drives M1 further into saturation and M2 towards the linear/triode region

Is this understanding correct? Am I thinking about these circuits in the correct way? I've been following Razavi's Design of Analog Integrated Circuits Book.

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  • \$\begingroup\$ @Oldfart My apologies. I updated it now. Thanks \$\endgroup\$ Jan 7, 2020 at 1:09

1 Answer 1

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You need to realize that M1 and M2 both want to behave as a current source. Also, M1 and M2 are in series so their current must be the same. Which device (M1 or M2) determines the current depends on which device wants to make the smallest current. If M1 wants 100 uA to flow but M2 wants 110 uA to flow then M1 will "win" and 100 uA will flow. Then M2 will be forced into linear mode.

Theoretically there can be a situation where both M1 and M2 are in saturation and both want the exact same current to flow. But this is purely theoretical, in the real world the currents are never identical so in practice one transistor is in saturation and the other is in linear mode (it is possible to use a DC feedback loop to force both transistors in saturation but that requires a more complex circuit).

Phase 1

  • Iref = 100uA.
  • Due to the 1:1 ratio between M3 and M2, 100uA flows through M2 and M1.

That's not entirely correct, M2 wants to make 100 uA flow, it depends on M1 if that's going to happen.

If M1 is set to slightly more than 100 uA, for example 101 uA, then M2 will "win" and 100 uA will flow. M1: linear mode, M2: saturation mode

If M1 is set to slightly less than 100 uA, for example 99 uA then M1 will "win" and 99 uA will flow. M1: saturation mode, M2: linear mode

Phase 2

  • Iref increases to 200uA.
  • Due to the 1:1 ratio between M3 and M2, 200uA flows through M2 and M1
  • M1 has a bias voltage on it's gate to support only 100uA, so the drain-source voltage of M1 (=Vout) must increase to support this new 200uA current.

If a transistor saturates at 100 uA then you cannot and should not (try to) increase its \$V_{DS}\$ to a higher value so that more current will flow. You would need more than the breakdown voltage of the transistor and that could potentially damage it! Usually the maximum \$V_{DS}\$ you can apply is the supply voltage and usually this supply voltage has a value of less than the breakdown voltage. So: you cannot make 200 uA flow, 100 uA will flow because that's what M1 allows.

  • This drives M1 further into saturation and M2 towards the linear/triode region

M2 will try to make 200 uA flow but M1 limits the current to 100 uA so M2 has no choice other than to go into linear mode.

Phase 2 Alternative Understanding

  • Iref increases to 200uA.
  • Due to the 1:1 ratio between M3 and M2, 200uA flows through M2 and M1
  • As M1 has a fixed gate-source voltage, it can be seen as a fixed ressitance with resistance of ro1.

No this is not the case, A fixed \$V_{GS}\$ does not mean that the MOSFET has a fixed resistance! Also, ro1 is a small signal parameter which is irrelevant now since we're dealing with large signal or DC behavior.

Your ## Phase 2 Alternative Understanding ## is wrong and not a proper explanation of the circuit's behavior.

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  • \$\begingroup\$ Great Response. Razavi's video says that current will increase in the right branch. youtu.be/gjKTAx9FQHo at time 40:50. Did he make a mistake then? He said that the current in left branch increeases, so current in the right branch increases too, and if you consider M1 as an impedance, there will be a higher voltage drop across it. \$\endgroup\$ Jan 7, 2020 at 13:05
  • \$\begingroup\$ Mr. Razavi is skipping some things, he's considering the point where the output changes (from low to high voltage) and then indeed the current increase in the mirror will increase the output voltage. Under a static condition (all voltages do not change over time) then indeed you can consider M1 as "an impedance". Do \$V_{DS}/I_D\$ and you get a certain resistance. However, if you change the current \$I_D\$ and calculate again that resistance will have a different value. The "impedance" analysis is OK to see if a voltage/current increases or decreases but no more than that. \$\endgroup\$ Jan 7, 2020 at 13:15
  • \$\begingroup\$ Hmm. Razavi said that the current in the right branch increases for a change in the reference, however in your explanation, you're saying that the current in the right branch does not increase. \$\endgroup\$ Jan 7, 2020 at 14:03
  • \$\begingroup\$ You're comparing apples and pears, what I was talking about is evaluating what the state of the circuit is in a certain situation. What Razavi was talking about is what happens to the state of the circuit when voltages/currents change. \$\endgroup\$ Jan 7, 2020 at 15:15
  • \$\begingroup\$ Sorry. I'm still quite not understanding. If the reference current increases from 100uA to 200uA like Razavi's step increase, M3 will happily provide 200uA as the gate has down. M2 will now try to provide 200uA as it's gate has gone down too. However, M1 is fixed to 100uA and so the output voltage increases, thus pushing M1 further into saturation and M2 into triode (drain voltage has increased for M2). So, now current in the right branch is still at 100uA and output voltage has gone up. How is Razavi then saying that the current in the right branch increases? \$\endgroup\$ Jan 7, 2020 at 17:04

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