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The ADS4126 is a 12-Bit, 160-MSPS Analog-to-Digital Converter (ADC). Its data rate is too high for it to be read out using something like SPI or I2C. It does use SPI for control purpose though.

The output of this ADC is parallel but can be configured to be either DDR LVDS or basic parallel CMOS. My questions are as follows:

  1. Do ultra low power DSPs exist that can interface with an ADC that has a parallel DDR LVDS output?
  2. Is the CMOS output intended for DSPs and the DDR LVDS for interface with ASIC or FPGAs?
  3. Is the ADC not capable of same maximum data rate when used with CMOS output? It does seem like it from the datasheet but it is not mentioned in the front page that this is so.
  4. What is the purpose of giving the Standard Swing, Low Swing, Default Strength and 2x Strength of the DDR LVDS interface on the front page?
  5. Why is it important that we may able to control the default strength and output strength of the DDR LVDS output?
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  1. Do ultra low power DSPs exist that can interface with an ADC that has a parallel DDR LVDS output?

Define "ultra-low". obviously, your DSP needs to deal with nearly 2 Gb/s of sample data, so this can only be relatively low power, right? Sounds like a laptop CPU to me...

  1. Is the CMOS output intended for DSPs and the DDR LVDS for interface with ASIC or FPGAs?

yes. And no. You'll find either on either.

  1. Is the ADC not capable of same maximum data rate when used with CMOS output? It does seem like it from the datasheet but it is not

Well, then trust the datasheet!

Driving CMOS takes a lot of power, and thus implies a limited switching speed. Thus, it'd be an unusual design decision to have a CMOS receiver for 160 Mbd.

mentioned in the front page that this is so.

  1. What is the purpose of giving the Standard Swing, Low Swing, Default Strength and 2x Strength of the DDR LVDS interface on the front page?

Well, guess what: defining the voltage swing and drive strength to suit your application!

  1. Why is it important that we may able to control the default strength and output strength of the DDR LVDS output?

For longer, lossy traces on a PCB a higher voltage swing might be necessary for the signal to still be well-defined at the receiver.

To drive a lower load, e.g. for noise reduction, a stronger drive is desirable, which is not desirable when you drive with the normal transmission line wave impedance.

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  • \$\begingroup\$ DSPs may be able to read CMOS output of the ADC but I have not yet found one (through my quick google search) that has capability to read the DDR LVDS output from the ADC. \$\endgroup\$ – Quantum0xE7 Jan 8 at 10:28

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