The ADS4126 is a 12-Bit, 160-MSPS Analog-to-Digital Converter (ADC). Its data rate is too high for it to be read out using something like SPI or I2C. It does use SPI for control purpose though.
The output of this ADC is parallel but can be configured to be either DDR LVDS or basic parallel CMOS. My questions are as follows:
- Do ultra low power DSPs exist that can interface with an ADC that has a parallel DDR LVDS output?
- Is the CMOS output intended for DSPs and the DDR LVDS for interface with ASIC or FPGAs?
- Is the ADC not capable of same maximum data rate when used with CMOS output? It does seem like it from the datasheet but it is not mentioned in the front page that this is so.
- What is the purpose of giving the Standard Swing, Low Swing, Default Strength and 2x Strength of the DDR LVDS interface on the front page?
- Why is it important that we may able to control the default strength and output strength of the DDR LVDS output?